Comments (7)
I've tried to change this, hope it's better.
from misoc.
I don't think the name uart.wishbone
is relevant. Those names should reflect the role that the UART has, either as a target device that receives the characters to write from a CPU through a bus (Wishbone, CSR, ...), or as an initiator device that masters a bus.
from misoc.
Maybe uart.UART
for the normal CSR target peripheral (since this is the most common, default, assumed role of a UART in a SoC), and uart.bridge.Wishbone
for the initiator/bridge.
from misoc.
Thanks, so is it OK if I rename wishbone.py in bridge.py ? (I want to avoid creating a bridge directory for now since we only have a wishbone bridge, eventually later if we have others bridges (AXI, Avalon))
from misoc.
Sounds good.
from misoc.
Done, thanks for the feedback!
from misoc.
Thanks for fixing it!
from misoc.
Related Issues (20)
- Wrong version in `setup.py`
- different clocking of differentiator and integrator HOT 3
- misoc@2022-04-07 fail with either latest migen built from source (2022-09-02) and with migen 0.9.2 HOT 1
- replace liteeth _preamble_crc CSR with constant
- fix liteeth error counter atomicity problem HOT 2
- liteeth: remove dw parameterization HOT 2
- liteeth: rename dv to rx_dv
- liteeth: remove MII clock output
- clean up memory regions, names, offsets
- kasli/spi_flash: investigate and implement quad i/o read
- DDR3-related error in Vivado timing report for Ultrascale HOT 1
- spi: first half-cycle (setup period) of a chained, pure read uses the write divider instead of the read divider
- Record.connect return value not used HOT 3
- Binutils compilation
- Standard 1 bit SPI mode for spi_flash not available? HOT 2
- software not rebuilt after gateware change
- fix or remove Ultrascale SDRAM init HOT 4
- Wanted to Build a small SoC HOT 1
- CSRStorage with write_from_dev=True seems broken in simulation HOT 3
- register_rom weirdness HOT 2
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