Comments (9)
Similar issue with Vivado:
ERROR: [Synth 8-1766] cannot open include file lm32_config.v [C:/Python34/lib/si
te-packages/misoc-1.0-py3.4.egg/misoc/cores/lm32/verilog/submodule/rtl/lm32_incl
ude.v:61]
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Does the file exist:
C:/Python34/lib/site-packages/misoc-1.0-py3.4.egg/misoc/cores/lm32/verilog/submodule/rtl/lm32_include.v
from misoc.
In fact that's lm32_config.v that is missing in C:/Python34/lib/site-packages/misoc-1.0-py3.4.egg/misoc/cores/lm32/verilog.
It works fine when putting it manually there.
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Ok. Both with ISE and Vivado?
from misoc.
I actually cannot test setup.py because python 3.5 or the version of setuptools that comes with it in the arch linux packages borked the installation of data directories...
from misoc.
It's fine with ISE & Vivado yes. I can look at it, where is the code responsible for the copy of lm32_config.v?
from misoc.
766b0be should fix the problem.
from misoc.
Thanks, fixed!
from misoc.
👍 Thanks for testing!
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Related Issues (20)
- Wrong version in `setup.py`
- different clocking of differentiator and integrator HOT 3
- misoc@2022-04-07 fail with either latest migen built from source (2022-09-02) and with migen 0.9.2 HOT 1
- replace liteeth _preamble_crc CSR with constant
- fix liteeth error counter atomicity problem HOT 2
- liteeth: remove dw parameterization HOT 2
- liteeth: rename dv to rx_dv
- liteeth: remove MII clock output
- clean up memory regions, names, offsets
- kasli/spi_flash: investigate and implement quad i/o read
- DDR3-related error in Vivado timing report for Ultrascale HOT 1
- spi: first half-cycle (setup period) of a chained, pure read uses the write divider instead of the read divider
- Record.connect return value not used HOT 3
- Binutils compilation
- Standard 1 bit SPI mode for spi_flash not available? HOT 2
- software not rebuilt after gateware change
- fix or remove Ultrascale SDRAM init HOT 4
- Wanted to Build a small SoC HOT 1
- CSRStorage with write_from_dev=True seems broken in simulation HOT 3
- register_rom weirdness HOT 2
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