LiteEth: Add support for RGMII phy interface about misoc HOT 3 CLOSED

Yes that's something we plan to add and that would also be a nice contribution.
It should be very similar to GMII with only DDR support to input/output data.

If you want to add it, create your rgmii.py file, use GMII as a starting point and add the DDR stuff to it (IDDR2/ODDR2 on Xilinx devices). Also please try to indicate in the code where it's vendor specific, and where it's generic so that it will ease contribution for others FPGA vendors.

If you do it, please send us your rgmii.py as a patch, we will review it and integrate it.

from misoc.

I'm pretty sure this has been done by @enjoy-digital (https://github.com/enjoy-digital/liteeth/blob/master/liteeth/phy/s6rgmii.py)
liteEth has been moved into a separate repo again (https://github.com/enjoy-digital/liteeth/blob/master) as part of the reorg in #17

from misoc.

Sorry, that link to liteeth should be https://github.com/enjoy-digital/liteeth

from misoc.