liteeth: MII clock frequency detection is hacky and unreliable about misoc HOT 5 CLOSED

Here's an example of a gateware frequency meter:
https://github.com/m-labs/tdc-core/blob/master/core/tdc_freqc.vhd
Double latching the counter output directly is correct here as the value has been stationary for enough cycles when it is read in the system clock domain.

from misoc.

Thanks for the feedback. I should have spent more time on that.

I've implemented another solution that in fact avoids most of the resynchronizations. (it only requires a pulse resynchronization from eth_rx to sys_clk).

For now it's still assisted by software, I will probably move all the detection to the gateware in the future.

from misoc.

That's better, but the software timing is still fragile (proportional to the execution time of just a few C statements); additionally, it breaks if you don't netboot the board or if you switch between MII and GMII modes after the board has booted (unless the runtime implements eth_mode_detection as well). Solving those problems correctly sounds more difficult than putting the mode switch in gateware.

from misoc.

OK, mode switch is now done in gateware (I've just kept the MII/GMII printf in software).
I've tested dynamic mode switch while pinging the board (unpluging the cable from a 100Mbps switch and plugging it to a 1Gbps switch, and the reverse).
Thanks for insisting.

from misoc.

Good, thanks a lot! 👍

from misoc.