Comments (5)
Here's an example of a gateware frequency meter:
https://github.com/m-labs/tdc-core/blob/master/core/tdc_freqc.vhd
Double latching the counter output directly is correct here as the value has been stationary for enough cycles when it is read in the system clock domain.
from misoc.
Thanks for the feedback. I should have spent more time on that.
I've implemented another solution that in fact avoids most of the resynchronizations. (it only requires a pulse resynchronization from eth_rx to sys_clk).
For now it's still assisted by software, I will probably move all the detection to the gateware in the future.
from misoc.
That's better, but the software timing is still fragile (proportional to the execution time of just a few C statements); additionally, it breaks if you don't netboot the board or if you switch between MII and GMII modes after the board has booted (unless the runtime implements eth_mode_detection as well). Solving those problems correctly sounds more difficult than putting the mode switch in gateware.
from misoc.
OK, mode switch is now done in gateware (I've just kept the MII/GMII printf in software).
I've tested dynamic mode switch while pinging the board (unpluging the cable from a 100Mbps switch and plugging it to a 1Gbps switch, and the reverse).
Thanks for insisting.
from misoc.
Good, thanks a lot!
from misoc.
Related Issues (20)
- Wrong version in `setup.py`
- different clocking of differentiator and integrator HOT 3
- misoc@2022-04-07 fail with either latest migen built from source (2022-09-02) and with migen 0.9.2 HOT 1
- replace liteeth _preamble_crc CSR with constant
- fix liteeth error counter atomicity problem HOT 2
- liteeth: remove dw parameterization HOT 2
- liteeth: rename dv to rx_dv
- liteeth: remove MII clock output
- clean up memory regions, names, offsets
- kasli/spi_flash: investigate and implement quad i/o read
- DDR3-related error in Vivado timing report for Ultrascale HOT 1
- spi: first half-cycle (setup period) of a chained, pure read uses the write divider instead of the read divider
- Record.connect return value not used HOT 3
- Binutils compilation
- Standard 1 bit SPI mode for spi_flash not available? HOT 2
- software not rebuilt after gateware change
- fix or remove Ultrascale SDRAM init HOT 4
- Wanted to Build a small SoC HOT 1
- CSRStorage with write_from_dev=True seems broken in simulation HOT 3
- register_rom weirdness HOT 2
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