m-labs / misoc Goto Github PK

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            Copyright 2007-2023 / M-Labs Ltd
            Copyright 2012-2015 / Enjoy-Digital

 the original high performance and small footprint SoC based on Migen

[> Features
-----------
 * Multiple CPU options:
   * VexRiscV.
   * mor1kx (a better OpenRISC implementation).
   * LatticeMico32, modified to include an optional MMU (experimental).  
 * Supports SDR, DDR, LPDDR, DDR2 and DDR3.
 * Provided peripherals: UART, GPIO, timer, NOR flash controller, SPI flash
   controller, Ethernet MAC, and more.
 * High performance: on Kintex-7, 125MHz system clock frequencies,
   64Gbps DDR3 SDRAM bandwidth.
 * Low resource usage: basic implementation fits easily in Spartan-6 LX9.
 * Portable and easy to customize thanks to Python- and Migen-based
   architecture.
 * Design new peripherals using Migen and benefit from automatic CSR maps
   and logic, etc.
 * Possibility to encapsulate legacy Verilog/VHDL code.

MiSoC comes with built-in targets for a few boards. Support for other boards can 
easily be added as external modules.

[> License
----------
MiSoC is released under the very permissive two-clause BSD license. Under
the terms of this license, you are authorized to use MiSoC for
closed-source proprietary designs.
Even though we do not require you to do so, those things are awesome, so please
do them if possible:
 * tell us that you are using MiSoC
 * cite MiSoC in publications related to research it has helped
 * send us feedback and suggestions for improvements
 * send us bug reports when something goes wrong
 * send us the modifications and improvements you have done to MiSoC.

See LICENSE file for full copyright and license info.

[> Links
--------
Web:
  https://m-labs.hk

Public forum:
  https://forum.m-labs.hk