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The current VexRISCV configuration works well on big FPGAs like the Artix-7 and Spartan 6 but is too big for the tiny iCE40 based devices.

It would be good to add a variant which works well on the iCE40, two options seem to exist;

VexRiscv small and productive (RV32I, 0.82 DMIPS/Mhz)  ->
  Artix 7    -> 327 Mhz 698 LUT 558 FF
  Cyclone V  -> 158 Mhz 524 ALMs
  Cyclone IV -> 146 Mhz 1,061 LUT 552 FF
  iCE40      -> 55 Mhz 1541 LC

VexRiscv small and productive with I$ (RV32I, 0.72 DMIPS/Mhz, 4KB-I$)  ->
  Artix 7    -> 331 Mhz 727 LUT 600 FF
  Cyclone V  -> 152 Mhz 536 ALMs
  Cyclone IV -> 156 Mhz 1,075 LUT 565 FF
  iCE40      -> 54 Mhz 1686 LC

It probably good to steal the VexRISCV configuration from the MuraxSoC configuration;

Depending the CPU configuration, on the ICE40-hx8k FPGA with icestorm for synthesis, the full SoC has the following area/performance :

RV32I interlocked stages => 51 Mhz, 2387 LC 0.45 DMIPS/Mhz
RV32I bypassed stages => 45 Mhz, 2718 LC 0.65 DMIPS/Mhz
Its implementation can be found here: src/main/scala/vexriscv/demo/Murax.scala.

Hi,

VexRiscv 1.1 was just released. And improved/fix/added stuff :

• Compatible with mainline linux
• Write-throug data cache
• Better RISC-V CSR compliance
• Fix some bugs occurring when using both exception and interruptions.

If that's fine for you, i will merge it into VexRiscv-verilator.
Also if i do so, i would like to move the VexRiscv dependance from SBT to a regular git submodule.

[submodule "ext/VexRiscv"]
	path = ext/VexRiscv
	url = ../../SpinalHDL/VexRiscv.git

../../SpinalHDL/VexRiscv.git should probably be https://github.com/SpinalHDL/VexRiscv right?

Swapping between the Min and Lite variant produces drastically different results.

AFAICT the 'Min' variant is skipping some instructions, executing some of them twice (I see doubled up memory writes), ...

All on very simple design with just one bram connected to instruction port and one to the data port.

Has anyone run the -Min variant ?