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EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It is developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker under supervision by Prof. Dr.-Ing. Ralf Gessler.

License: MIT License

VHDL 86.07% Tcl 12.92% Makefile 0.03% C 0.34% SystemVerilog 0.61% Shell 0.01% Pascal 0.02%

edrico's Introduction

EDRICO

EDRICO is an open source RISC-V based processor developed during a students work at DHBW Ravensburg. RISC-V is an open source instruction set standard, developed by Berkely University. Due to the open nature of the architecture it has a high potential to become one of the big ISAs in years to come. Companys like Alibaba, Western Digital and Nvidia are currently increasing research on RISC-V based processors. Due to the predicted future market share of RISC-V processors, it would surely be interessting for students to work on the developement of an IP as well as corresponding software. Our goal is to develope a minimalist single core 32-bit integer RISC-V IP, to conduct some benchmarks on it in software and hardware (FPGA) and investigate the possibilties of software and hardware security features. Respecting the open nature of the ISA the IP will be openly available, thus constituting an interessting possibility for further student work.

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