Hardware-Accelerator-ASIC-for-Simplified-Convolutional-Neural-Network
Language: Verilog
Platforms: Modelsim, Synopsys Design Compiler.
• Designed a synthesizable ASIC implementing the two staged convolutional neural network arithmetic on inputs read from SRAM.
• The design was verified for functional correctness and synthesized to achieve minimum area and clock period.
• Major design innovation includes parallel memory access logic and pipelined computation of dot product which is responsible for reducing the design area and clock period.