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A Verilog synthesis flow for Minecraft redstone circuits

Java 9.84% Verilog 27.07% Shell 0.03% SystemVerilog 38.82% C++ 24.01% C 0.21% Batchfile 0.03%

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fabrichdl's Issues

Same track channel skips repeater, causing redstone signal decay

In general, when the code tries to connect two tracks, the channel will be at least 3 blocks wide, and a repeater will be placed in the middle to extend the redstone signal. However, there appears to be a case when the code tries to connect the same track to itself, which results in a 1-width block and no repeater. This can cause the redstone signal to decay and not reach further down the circuit.

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