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Grad school, Adv Computer Architecture, 4-way associative data cache project. A cache in the primary storage hierarchy contains cache lines that are grouped into sets. If each set contains k lines then we say that the cache is k-way associative. A data request has an address specifying the location of the requested data. Each cache-line sized chunk of data from the lower level can only be placed into one set. The set that it can be placed into depends on its address. This mapping between addresses and sets must have an easy, fast implementation. The fastest implementation involves using just a portion of the address to select the set.

C++ 99.04% C 0.96%
4waysetassociative computer-architecture cpp11 doxygen-documentation stl virtual-memory visualstudio2017

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