MIPSim is a MIPS (Microprocessor without Interlocked Pipeline Stages) processor simulation project designed in VHDL (VHSIC Hardware Description Language). This project aims to provide a detailed implementation of the MIPS processor.

• Complete simulation of a 32-bit MIPS processor.
• Support for essential MIPS instructions for computation and flow control.
• Modular architecture for easy understanding and extension.
• Testbenches included for functionality validation.

• A VHDL environment (e.g., GHDL, ModelSim).
• A text editor or IDE supporting VHDL.

Contributions are welcome, whether they are extensions, bug fixes, or improved documentation.

This project is licensed under the MIT License. Please see the LICENSE file for more details.

• muhamm-ad · GitHub