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1st-claas

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

2-d-fir-filter-design

5-days-vsd-low-power-using-ngspice

5 DAYS LOW POWER DESING WORKSHOP USING NGSPICE

adder

reversible floating point adder

adder-models-for-approximate-computing

This repository includes python modules to handle integer and floating point data and process them with exact and approximate adders. The crude input in decimal form is converted into standard binary representations and then processed. The errors incorporated can directly be monitored for analyzing the performance of the approximate design.

adder_networks

Store of prefix tree adder HDL, diagrams, and implementation results

addercircuitgenerator

This script generates and analyzes prefix tree adders.

advanced-system-on-chip-design-education-kit

Advanced System on Chip Design Education Kit

alterade2labs_verilog

My solutions to Alteras example labs

approx-fpgas

Approximate arithmetic circuits for FPGAs

approximate-1d-dct-architecture

This is a Verilog implementation of pipelined architecture for the computation of 1D 8-point DCT. This is an approximate architecture which uses only 12 adders and no multipliers for the whole computation.

approximate-8x8-multiplier-designs

Implementation of approximate 8x8 multipliers using 4x4 multipliers with 4:2 compressor.

approximate_multiplier

area-optimized-shift-and-add-multiplier

Module and testbench codes are given in Verilog for a low-cost synchronous, generic multiplier that uses only one adder with bit width as same as its inputs' bit width.

asic--vlsi_design_flow_lectures

asterics

ASTERICS - An Open Toolbox for Sophisticated FPGA-Based Image Processing

astrosoft

Astrosoft is a free Indian Astrology software program for Astrologers.

augmented-reality-on-fpga

avsdbgp_3v3_sky130_v1

avsdbgp_3v3_sky130_v2

avsdcmp_3v3_sky130

avsddac_3v3_sky130_v1

avsddac_3v3_sky130_v2

avsdopamp_3v3_sky130_v2

avsdpll_1v8

8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

avsdpll_1v8_sky130_ss

basic-static-timing-analysis

block_based_circuit_design

GSoC 2021, FOSSi Foundation

book-chapter-publications_-high-level-synthesis-of-finger-print-authentication-system-

High-Level-Synthesis-of-Finger-Print-Authentication-System

book-python-programming-problem-solving-packages-and-libraries

Python book