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fir_filter-fault-tolerant

N-modular redundancy FIR Filter with fault modeling and injection

fir_filter_design

FIR

fir_filter_design-1

This repository contains two filters implemented in verilog. One of them use folding to minimize the area while the other uses systolic arrary to enlarge the throughput.

firfilt

Routines for designing Windowed Sinc, Parks-McClellan and Moving Average Finite Impulse Response (FIR) filters and filtering EEGLAB EEG datasets. The routines for designing Parks-McClellan FIR filters require the MATLAB Signal Processing Toolbox. Report bugs, unexpected behavior and feature requests to widmann at uni-leipzig dot de.

firhdlcodegenerator

Codes for our paper "Automated N-tap 1&2&3 Phase Low-pass Filter HDL Code Generation"

fpga

FPGA projects and IPs

fpga-fir-filter

Lecture about FIR filter on an FPGA

fpga-imaging-library

An open source library for image processing on FPGA.

fpga-stuff

classwork for ECE417 - DSP hardware design

fpga_image_processing

Image capture, image filtering and image display (VGA) : picture in picture, edge detection, gray image and smooth image

fpga_image_processing-1

IP operations in verilog (simulation and implementation on ice40)

fpgasimulation

Example files for the book FPGA SIMULATION

g_best-guided-cuckoo-search-algorithm

[A PART OF MY BACHELOR THESIS] Efficient Design of FIR filter using G_best Guided Cuckoo Search Meta-heuristic Algorithm

generic-fir-filter-using-vhdl

github-slideshow

A robot powered training repository :robot:

han-carlson-adder

code for printing verilog code of han carlson adder for n bits in python as well as java both.

hardware-description-languages-for-fpga-design

My HDL activities appear here. This is for my personal use. PPT's copyrights to University of Colorado Boulder.

hardware_implementation_of_rgb_to_gray

【Verilog&vivado】彩色图像转灰度的硬件实现

hdl

high-speed-recursive-ling-adder

A deep research in binary 2^n-1 Adders. And an implementation of various hybrid resursive Ling adders.

image-classification-using-cnn-on-fpga

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

image-processing-

CS203 Course Project using verilog

image_processing_verilog

Parameterized Verilog code for Image Sharpening (Laplacian Filter) and Image smoothening (Average Filter) on 128x128 image

imageprocessing1

Using Verilog HDL and Altera ModelSim to process RGB image to Gray.

implementation-of-arithmetic-adders-performance-comparison-using-xilinx-vivado

Ripple Carry Adders, Carry Select Adders, Carry Lookahead Adders

introduction-to-soc-design-education-kit

Introduction to SoC Design Education Kit

ladner-fischer-adder

A parallel prefix adder used in pentiun 4 machines made for a microelectronic project at polytechnic of Turin

ladner_fischer_adder

Verilog HDL CODE

libero-soc-design-suite-tcl-examples

Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.

linux-commands-for-vlsi-engineers

Below are basic Linux command which may be useful for VLSI Engineers while working in Linux