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A localized wireless communication system capable of transmitting and receiving data packets to and from peer systems. This project was developed in SystemVerilog and deployed to an FPGA board.

SystemVerilog 0.98% Verilog 5.38% VHDL 88.14% V 5.08% Pascal 0.01% Stata 0.02% Shell 0.20% Forth 0.01% Tcl 0.07% JavaScript 0.04% Batchfile 0.01% C 0.06% HTML 0.02% PureBasic 0.01%
systemverilog fpga wireless-communication uart-interface manchester-encoding

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