OCT-FPGA templated project for research in Nextlab

Makefile 0.06% C++ 23.90% C 0.67% LLVM 0.53% Ada 47.12% Tcl 3.37% Verilog 8.76% VHDL 14.24% Shell 0.01% SystemVerilog 1.34%

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dummy `bridge.cpp` inside bit container 1 (tail node)

I notice this weird bridge kernel inside bit container 1

// kernel_src/bit_container_1/bridge.cpp
void bridge(hls::stream<pkt>& stream_in, hls::stream<pkt>& stream_out){
#pragma HLS interface ap_ctrl_none port=return
#pragma HLS PIPELINE II=1 style=flp
	pkt temp;
	stream_in >> temp;
	stream_out << temp;

}
}

It will cause the following error when compiling kernels into XO objects

ERROR: [CFGEN 83-2284] No stream resources found that can accomodate compute unit "bridge_1.stream_in"ERROR: [SYSTEM_LINK 82-36] [23:08:51] cfgen failedTime (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 2177.324 ; gain = 0.000 ; free physical = 68168 ; free virtual = 102523ERROR: [SYSTEM_LINK 82-62] Error generating design file for /home/sx233/OCT_FPGA_Project_Template_for_Nextlab/build/bit_container_1/vivado/link/sys_link/cfgraph/cfgen_cfgraph.xml, command: /tools/Xilinx/Vitis/2021.2/bin/cfgen  -nk cmac_0:1:cmac_0 -nk networklayer:1:networklayer_0 -nk packet_p2s:1:packet_p2s_0 -nk packet_s2p:1:packet_s2p_0 -nk packet_switch:1:packet_switch_0 -nk auto_data_pack:1:auto_data_pack_0 -sc cmac_0.M_AXIS:networklayer_0.S_AXIS_eth2nl -sc networklayer_0.M_AXIS_nl2eth:cmac_0.S_AXIS -sc networklayer_0.M_AXIS_nl2sk:packet_switch_0.stream_in -sc packet_switch_0.stream_out:packet_p2s_0.stream_in -sc packet_p2s_0.stream_out:packet_s2p_0.stream_in -sc packet_s2p_0.stream_out:auto_data_pack_0.stream_in -sc auto_data_pack_0.stream_out:networklayer_0.S_AXIS_sk2nl -slr cmac_0:SLR2 -slr networklayer_0:SLR2 -dmclkid 0 -r /home/sx233/OCT_FPGA_Project_Template_for_Nextlab/build/bit_container_1/vivado/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/sx233/OCT_FPGA_Project_Template_for_Nextlab/build/bit_container_1/vivado/link/sys_link/cfgraph/cfgen_cfgraph.xml
ERROR: [SYSTEM_LINK 82-96] Error applying explicit connections to the system connectivity graph
ERROR: [SYSTEM_LINK 82-79] Unable to create system connectivity graph
INFO: [v++ 60-1442] [23:08:51] Run run_link: Step system_link: Failed
Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 2070.332 ; gain = 0.000 ; free physical = 68207 ; free virtual = 102562
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
Makefile:132: recipe for target '../../build/bit_container_1/bit_container_1.xclbin' failed
make[1]: *** [../../build/bit_container_1/bit_container_1.xclbin] Error 1
make[1]: Leaving directory '/home/sx233/OCT_FPGA_Project_Template_for_Nextlab/kernel_src/bit_container_1'
Makefile:112: recipe for target 'bit_container_1' failed
make: *** [bit_container_1] Error 2

It seems that it is not connected to any other components; so I suppose I only need to remove it?

HEAD node Rx deadlock

Hi,

I am trying a simplified version with two FPGAs to realize the loopback: it is basically the HEAD node + TAIL node (as I cannot reserve more than 2 FPGAs on OCT as of now)

Here is what I did. First, I compiled the bitstreams bit_container_0.xclbin for HEAD node and bit_container_1.xclbin for TAIL node using Vitis 2021.2 (along with other host binaries to set up IP address)

Second, I changed the INI configuration, connecting from HEAD(192.168.2.10:50000) to TAIL (192.168.2.20:60000)

# head_ip.ini
192.168.2.10
50000:192.168.2.20:60000

# tail_ip.ini
192.168.2.20
60000:192.168.2.10:50000

and Finally, I copied the files to OCT cloud nodes, and run the following commands

# Setup the HEAD node IP on node0@pc-155
sx233@node0:~$ ./udp_setup bit_container_0.xclbin head_ip.ini 
Using FPGA binary file specfied through the command line: bit_container_0.xclbin 
Setting up CMAC 0
Get user specified IP address: c0a8020a
Get 00th socket conncection 192.168.2.10:50000 <->  192.168.2.20:60000
Using gateway: c0a802ff
Using MAC: f1f2f3f40a
Loading bit_container_0.xclbin 
Device name:  xilinx_u280_xdma_201920_3
Device bdf:   0000:3b:00.1
There are 16 hardware sockets.
ARP valid entry found at 20
TX status 0
RX status 3
Link is as active!

Then set up the TAIL node IP on node1@pc-158

sx233@node1:~$ ./udp_setup bit_container_1.xclbin tail_ip.ini
Using FPGA binary file specfied through the command line: bit_container_1.xclbin 
Setting up CMAC 0
Get user specified IP address: c0a80214
Get 00th socket conncection 192.168.2.20:60000 <->  192.168.2.10:50000
Using gateway: c0a802ff
Using MAC: f1f2f3f414
Loading bit_container_1.xclbin 
Device name:  xilinx_u280_xdma_201920_3
Device bdf:   0000:3b:00.1
There are 16 hardware sockets.
ARP valid entry found at 10
TX status 0
RX status 3
Link is as active!

# and run `./tail_bin bit_container_1.xclbin ` to enable auto-data-pack (I suppose?)
sx233@node1:~$ ./tail_bin bit_container_1.xclbin 
Using FPGA binary file specfied through the command line: bit_container_1.xclbin 
Send 704 Bytes to Sokcet 0
All kernel finished!

In the very end, I go back to HEAD node to transmit data

sx233@node1:~$ ./head_bin bit_container_0.xclbin 704
Using FPGA binary file specfied through the command line: bit_container_0.xclbin 
Send 704 Bytes to Sokcet 0
File alice29.txt read!
All kernel started!
All kernel finished!
All kernel started!
All kernel finished!
************************************************











************************************************

It receives no data, and the CU kernel on node1's FPGA is deadlocked.

ngdxzy / oct_fpga_project_template_for_nextlab Goto Github PK

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oct_fpga_project_template_for_nextlab's Issues

dummy `bridge.cpp` inside bit container 1 (tail node)

HEAD node Rx deadlock

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