Comments (2)
olofk
commented on July 3, 2024
That would be a good addition. Unfortunately I know too little about Vivado HLS. Wondering if it would be best done as a completely new edalize backend or if it would be better to have as a generator that just compiles the code to RTL and reuses the rest of the infrastructure after that
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eine
commented on July 3, 2024
Wondering if it would be best done as a completely new edalize backend or if it would be better to have as a generator that just compiles the code to RTL and reuses the rest of the infrastructure after that
I think that this depends on the project. It is possible to export HLS designs to RTL (VHDL) and then simulate them with GHDL + VUnit verification components. However, the software partition might need rewriting.
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Related Issues (20)
- Xcelium: file list HOT 1
- Modelsim missing in tools
- Support a Vivado IP-packaging flow HOT 2
- Simulating Vivado IPs (xci, bd) HOT 4
- `make_libraries_directories` on Windows fails due to `mkdir -p` HOT 3
- GHDL Support for cocotb simulation flow HOT 2
- Vars do not survive Edaflow
- Add update_compile_order to vivado workflow HOT 1
- QSys Pro 23 files are not processed correctly by the filter HOT 4
- Jinja2 issue witth edarool loader HOT 4
- Vivado flow not re-run when Verilog parameter is changed HOT 3
- Yosys: `configure_main` should check for "file_type" in fileset, or provide a default
- Incorrect toplevel name used when loading EDIF netlist in Vivado
- How to read an EDIF netlist into Vivado that isn't the toplevel?
- Not possible to fully suppress stdout in edatool API?
- Passing Verilog string parameters with quotes
- edalize/flows/edaflow.py # Yeah, I know. It's just a temporary hack HOT 1
- Symbiflow tool doesn't pass Yosys parameters when using VPR as PnR HOT 1
- Error using f4pga flow for Xilinx
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