CH3/simple_ff_async/tb/tb.sv - currently this file contains test code from the CH2 chapter

Hi,

I am reading your book and I am trying to run simulation on Vivado 2022.1 for CH1's logic_ex example. However, it fails on checking and show "FAIL: AND Gate mismatch". I tried to set Project device to Nexys A7-100T and Arty A7-100, and the results are same. I wonder if you may advise.

A bug in the author's Moore state machine program: undefined EQUAL state, causing the program to remain in WAIT4BUTTON state and crash.
add after line 61

last_op[Center]: state<=EQUAL;

add after line 80

EQUAL: begin
  last_op<=op_store; // Store our last operation
  state<=WAIT4BUTTON;
end

Should be difference of, not sum of

Should be difference of, not sum of

Should be product of, not difference of

in the traffic_light.sv,
localparam COUNT_1S = int'(100000000 / CLK_PER); localparam COUNT_10S = 10 * int'(100000000 / CLK_PER);
because of 1s=1,000,000,000, so the code above lack of one 0.
and all the code don't include the localparam COUNT_1S, in the line 82 and 99 the COUNT_10S should change to COUNT_1S.

In the book it is said:

Important note
To give you a jumpstart, all the projects in this book come complete with pre�set-up project files. Please see the appendix for instructions on setting up the 
first project in both project mode and non-project mode. This will guide you 
for setting up your own projects in the future.

I saw the errata but nothing in this folder is explaining how to setup a new project. Am I missing something?

First of all I want to thank you for the book and its accompanying resources. Great introduction to FPGA programming!

I'm using Vivado 2023.2, and had it transform the project to its new directory structure.

When simulating the pdm_audio project I get the following sine in data_in:

After fixing this, it turns out that the interleaved sampling is not working as I expected.
The counter[0] and counter[1] signals are used such that the resulting amplitude_valid signal of one can even coincide with that of the other, resulting in an amplitude signal that is not ideal.
Hopefully the difference is clear in the following image:
Sampling not fixed:

Sampling fixed:

After fixing that, the resulting amplitude signal still had some weird bumps in it:

During analysis of this behavior I concluded that the sample_counter can overflow because it is a 7 bit counter, but there is an overflow occurring if all 128 m_clk ticks that it is counting m_data is asserted.
I fixed this by reducing the number of m_clk ticks that m_data is added to sample_counter.

Then the resulting data_in and amplitude signals are as follows:

I will see if I can create a Pull Request for this.