padarom / pca-one Goto Github PK

Clock speed should be adjustable (e.g. via a rotary encoder). Maximum astable frequency of the used ICM7555 is 500kHz. The following options I have already considered:

C	R1	R2	Frequency	Duty Cycle	Time High	Time Low
1 nF	1 kΩ	2.2kΩ	267 kHz	59%	2.218µs	1.525µs
1 nF	220 kΩ	480 kΩ	1.224 kHz	59%	478.170µs	325.710µs
5 nF	2 MΩ	4.7 MΩ	25.316 Hz	59%	23.215ms	16.285ms
100 nF	2 MΩ	2 MΩ	2.405 Hz	67%	277.200ms	138.600ms

Evaluate 512 KiB RAM support, which requires 19 address lines. Implementation could be similar to i8086 with offset/segment registers.

http://i8086.de/adressen/adressen.html

https://www.reichelt.de/DRAM-FRAM-SRAM/AS-6C4008-55PCN/3/index.html?ACTION=3&LA=2&ARTICLE=146553&GROUPID=2954&artnr=AS+6C4008-55PCN&trstct=pol_4

https://www.reichelt.de/DRAM-FRAM-SRAM/CY62148ELL-55SX/3/index.html?ACTION=3&LA=2&ARTICLE=146556&GROUPID=2954&artnr=CY62148ELL-55SX&trstct=pol_6

https://www.arrow.de/products/5962-8959835mza/cypress-semiconductor ?

• - Requires more complicated address segmentation
• - Requires separate (19/20-bit) address bus
• - Requires more specialized registers (minimum 2, ideally 3-4)
• + Increases amount of RAM by 8-fold, massively increasing possible software
• + Allows for an extension of up to 1 MiB of RAM