Related Issues (17)
- Add AXI4-Lite Bridge Module HOT 2
- Tests for AXI2CSR
- DT Overlay Generator HOT 3
- AXI2CSR W/ 16 Bits Bus HOT 1
- CSR Shall Be Word Aligned
- misoc.interconnect.stream -> DMAC | PRI HOT 4
- Consider rename from migen-formal to migen-axi or migen-zynq HOT 3
- Is anyone working on this project a Uni student? HOT 2
- Expose `dma[:].rst_n` from `PS7`
- Add Documentation
- High-Speed DMA Controller Peripheral
- Migen platform compatibility HOT 1
- typo in soc_core.py
- compatibility with new MiSoC identifier core
- I would like use it with PYNQ board HOT 1
- Unbreak build and CI
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