peteut / migen-axi Goto Github PK

Add support for High-Speed DMA Controller Peripheral.

• wrap axi_dmac

Hello! I would like to know what is the status of the project. I want to use it but with PYNQ board. Do you have any documentation about how to use migen and vivado to make the hardware wrapper?

Thank you for your answer!

Kevin.

Add docstrings to modules, classes, refer to HOWTO_DOCUMENT.rst.txt.

• use ext.napoelon Sphinx plugin

adr[2:] to be used to connect.

Generate DT overlay from CSR meta data and clock specs.

• named iomem
• named irqs
• fclk, clock rate, name
• firmware name
  ...

Refer to litex-devicetree.

Migrate to use pyproject-tom.

Refer to B1.3, defined conversion mechanism

See ARM IHI 0022D.

It seems like there are currently mutiple efforts to interface Migen and LiteX with AXI + Zynq boards.

It would make this project a lot more findable if it was called something like migen-zynq or migen-axi.

Keep up the great work!

(("_".join([name, constant.name]).uppper(),
should be changed to upper

@PEtut - any chance you or any of your contributors are Uni students?

If so, I would love to see a Migen<->AXI/Zynq intergration proposal as part of the Google Summer of Code (were Google funds students to work on open source projects over their summer break).

The TimVideos, FOSSi Foundation and/or Apertus orgs would all probably be interested in accepting a project around this space if a good student applied!

• stream sink
• ignored EOP
• request burst transfer via DMAC | PRI

Refer to ARM DDI 0424D.

Replace identifier_mem with identifier in soc_core.py.

See also SpinalHDL implementation.

In tests/test_integration.py,

zedboard.Platform(name="soc", toolchain="vivado")

should be replaced with simply:

zedboard.Platform()

Those name and toolchain arguments have been removed from Migen.

• signal list B1.1.1
• bus width B1.1.2
• write strobes B1.1.3, memory access slaves must fully support write strobes
• optional signaling B1.1.4, shall support AXI IDs
• bridge requirements of AXI4-Lite slaves B1.2.1, requires AXI ID reflection
• direct connection requirements of AXI4-Lite slaves, B1.2.2, see B1.2.1

See ARM IHI 0022D.