Comments (13)
Also, are UInt types legacy? Why does the counter5mod2 have 5 uints rather than 5 bits?
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UInt types are not legacy, see https://github.com/phanrahan/magma/wiki/Types,-Operators,-and-Functions for some info on them
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@rdaly525 Looks like the issue is wiring the output of some arbitrary logic to a reset port of type coreir.rstIn
. Is there a way to "cast" types in coreir? (e.g. in this case, we want the output of an and
instance of type Bit
to be a coreir.rstIn
.
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@David-Durst Can't reproduce this with aetherling
, I get the following error
aetherling/modules/up.py:5: in <module>
from magma.coreirModuleWrapper import ModuleFromGeneratorWrapper
E ModuleNotFoundError: No module named 'magma.coreirModuleWrapper'
are you on a local branch for magma? Can you share that with me somehow? (easiest is to push the branch to the magma repo so I can just check it out)
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Please use the counterModMTest branch of aetherling. The counterModM test now doesn't require any of my changes to magma/pycoreir/coreir. I have some in all three repos that need to get pull requested in.
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On counterModM
, still getting
aetherling/modules/up.py:5: in <module>
from magma.coreirModuleWrapper import ModuleFromGeneratorWrapper
E ModuleNotFoundError: No module named 'magma.coreirModuleWrapper'
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The error indicates that it's trying to import something from magma
that I don't have
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Please pull and retry the test now. The includes should be removed now
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Also, here's the backtrace of the error from lldb.
(lldb) bt
* thread #1, queue = 'com.apple.main-thread', stop reason = signal SIGABRT
* frame #0: 0x00007fff6d58de3e libsystem_kernel.dylib`__pthread_kill + 10
frame #1: 0x00007fff6d6cc150 libsystem_pthread.dylib`pthread_kill + 333
frame #2: 0x00007fff6d4ea312 libsystem_c.dylib`abort + 127
frame #3: 0x00007fff6d4b2368 libsystem_c.dylib`__assert_rtn + 320
frame #4: 0x000000010506e185 libcoreir.dylib`CoreIR::Context::die() + 133
frame #5: 0x00000001051f933a libcoreir.dylib`CoreIR::ModuleDef::connect(CoreIR::Wireable*, CoreIR::Wireable*) + 4186
frame #6: 0x000000010466d147 libcoreir-c.dylib`COREModuleDefConnect + 71
frame #7: 0x00000001019f6884 libffi.6.dylib`ffi_call_unix64 + 76
frame #8: 0x00000001019f5e8b libffi.6.dylib`ffi_call + 939
frame #9: 0x000000010267bcf8 _ctypes.cpython-36m-darwin.so`_ctypes_callproc + 552
frame #10: 0x0000000102676222 _ctypes.cpython-36m-darwin.so`PyCFuncPtr_call + 242
frame #11: 0x0000000100009df1 python`_PyObject_FastCallDict + 177
frame #12: 0x0000000100163348 python`call_function + 392
frame #13: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #14: 0x00000001001635fc python`fast_function + 188
frame #15: 0x00000001001632ac python`call_function + 236
frame #16: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #17: 0x00000001001635fc python`fast_function + 188
frame #18: 0x00000001001632ac python`call_function + 236
frame #19: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #20: 0x0000000100154589 python`_PyEval_EvalCodeWithName + 425
frame #21: 0x00000001001636aa python`fast_function + 362
frame #22: 0x00000001001632ac python`call_function + 236
frame #23: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #24: 0x00000001001635fc python`fast_function + 188
frame #25: 0x00000001001632ac python`call_function + 236
frame #26: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #27: 0x00000001001635fc python`fast_function + 188
frame #28: 0x00000001001632ac python`call_function + 236
frame #29: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #30: 0x0000000100154589 python`_PyEval_EvalCodeWithName + 425
frame #31: 0x00000001001636aa python`fast_function + 362
frame #32: 0x00000001001632ac python`call_function + 236
frame #33: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #34: 0x0000000100154589 python`_PyEval_EvalCodeWithName + 425
frame #35: 0x0000000100163e15 python`_PyFunction_FastCallDict + 373
frame #36: 0x0000000100009e80 python`_PyObject_FastCallDict + 320
frame #37: 0x0000000100031468 python`method_call + 136
frame #38: 0x00000001000114ee python`PyObject_Call + 62
frame #39: 0x00000001000b3065 python`slot_tp_init + 117
frame #40: 0x00000001000b75b1 python`type_call + 241
frame #41: 0x0000000100009df1 python`_PyObject_FastCallDict + 177
frame #42: 0x0000000100163348 python`call_function + 392
frame #43: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #44: 0x00000001001635fc python`fast_function + 188
frame #45: 0x00000001001632ac python`call_function + 236
frame #46: 0x0000000100160f4c python`_PyEval_EvalFrameDefault + 47100
frame #47: 0x0000000100154589 python`_PyEval_EvalCodeWithName + 425
frame #48: 0x00000001001ac63c python`PyRun_FileExFlags + 252
frame #49: 0x00000001001abdee python`PyRun_SimpleFileExFlags + 366
frame #50: 0x00000001001d1dd6 python`Py_Main + 3718
frame #51: 0x0000000100001e7d python`main + 509
frame #52: 0x00007fff6d43e115 libdyld.dylib`start + 1
frame #53: 0x00007fff6d43e115 libdyld.dylib`start + 1
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Is this port supposed to be used as an asynchronous reset or a synchronous reset? If it is the latter, it is a bug. if it is the former, I have something called coreir.wrap which will wrap a bit into a named type.
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@rdaly525 if I understand correctly, a synchronous reset should use a standard bit
type, not the rst
named type.
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Yes, that is correct. It is on my TODO list to rename the rst type to "async_reset" or something like that
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Fixed by:
eab6f26
and
1b317d85ffa3c68dba1d85dc149bee4103456e39
phanrahan/magma@1b317d8
Will open a separate issue to resolve the RESET type semantics and matching them up with coreir
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Related Issues (20)
- Remove generated wrappers from coreir modules HOT 5
- Register should work with the _type parameter
- mantle Register not working HOT 2
- Bug In Mantle/CoreIR Simulation Of RAM HOT 2
- Unify coreir's commonlib and mantle
- Add logical and, or, not functions
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- [mantle primitives] Interface change proposal for logic HOT 5
- [primitives] generalizing width parameter interface to a type parameter interface HOT 2
- Cannot wire Mux2 HOT 6
- Regression with latest magma release HOT 2
- Reset priority for register HOT 6
- Mantle register cannot be properly reset HOT 5
- DefineAdd and DefineSub
- test failing HOT 1
- circuit.sequential mux issue
- Lots of depreciation warnings when using magma.circuit.combinational HOT 2
- Mantle generates deprecation warnings HOT 3
- Fix regfile for verilog backend HOT 3
- According to PEP 440 this wildcard syntax is no longer allowed HOT 1
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