Reversible logic is very effective and important in the formation of low power circuit.
The aim of low power VLSI circuits is to reduce the power dissipation.
It is called reversible when it reverses the output.
It is completely specified N-output, n-input Boolean function and it maps each output to a unique input and vice versa.
The reversible logic operations do not remove the information and has zero heat dissipation.
The circuit operates in a backward operation, allows reproducing the inputs from the outputs and consumes zero power.
A Feynman Gate is one such reversible gate.[1]
Feynman Gate is a 2×2 reversible logic gate.
The inputs are A, B, and the outputs are P, Q.
P=A gives the outputs of this gate, Q=A⊕B.
Thus the input A gets passed to P and Q gives the output as an XOR of A and B.
The Quantum cost of an FG is calculated to be 1.
Fan-out is not used in reversible logic.
Cab of the gate is used to get the desired net.
The corresponding circuit using MOSFETs has been as shown.
Here eight CMOS transistor has been used in this design.
The model can be used as an improved EXOR gate with a reversibility feature.
It can be easily verified from the output waveform that design works well for both forward and reverse directions.
There is also a CMOS pass transistor as shown in the figure M5 and M6 to pass the inputs. [2]
Note: The transmission gate using M24 nad M25 is soley used to separate the input and output just for the simulation purpose, to plot input and output separately.
* Generated for: PrimeSim
* Design library name: Feynman_gate
* Design cell name: Feynman_gate
* Design view name: schematic
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09
*Mon Feb 21 17:53:36 2022
.global gnd! vdd!
********************************************************************************
* Library : Feynman_gate
* Cell : Feynman_gate
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm24 p net80 a gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm7 net74 q b gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm6 q net74 b gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm5 net74 p gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm0 q b net74 gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm25 a gnd! p vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm4 p q b vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm3 q p b vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm2 q b p vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm1 net74 p net80 vdd! p105 w=0.1u l=0.03u nf=1 m=1
v26 net80 gnd! dc=1.8
v17 b gnd! dc=0.01 pulse ( 1.8 0 0.1n 0.1n 0.1n 2u 4u )
v18 a gnd! dc=0.01 pulse ( 1.8 0 0.1n 0.1n 0.1n 1u 2u )
.tran '1u' '20u' name=tran
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(a) v(b) v(p) v(q)
.temp 25
.option primesim_output=wdf
.option parhier = LOCAL
.end
* Generated for: PrimeSim
* Design library name: Feynman_gate
* Design cell name: Feynman_gate
* Design view name: schematic
.lib 'saed32nm.lib' TT
*Custom Compiler Version S-2021.09
*Mon Feb 21 17:41:35 2022
.global gnd! vdd!
********************************************************************************
* Library : Feynman_gate
* Cell : Feynman_gate
* View : schematic
* View Search List : hspice hspiceD schematic spice veriloga
* View Stop List : hspice hspiceD
********************************************************************************
xm24 p net80 a gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm7 net74 q b gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm6 q net74 b gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm5 net74 p gnd! gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm0 q b net74 gnd! n105 w=0.1u l=0.03u nf=1 m=1
xm25 a gnd! p vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm4 p q b vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm3 q p b vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm2 q b p vdd! p105 w=0.1u l=0.03u nf=1 m=1
xm1 net74 p net80 vdd! p105 w=0.1u l=0.03u nf=1 m=1
v26 net80 gnd! dc=1.8
v17 q gnd! dc=0.01 pulse ( 1.8 0 0.1n 0.1n 0.1n 2u 4u )
v18 p gnd! dc=0.01 pulse ( 1.8 0 0.1n 0.1n 0.1n 1u 2u )
.tran '1u' '20u' name=tran
.option primesim_remove_probe_prefix = 0
.probe v(*) i(*) level=1
.probe tran v(a) v(b) v(p) v(q)
.temp 25
.option primesim_output=wdf
.option parhier = LOCAL
.end
Thus, the input and output can be interchanged in the Feynman Gate and the functionality of the Feynman Gate is verified using 32nm Technology node of Synopsys.
- Synopsys Team/Company
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd. - [email protected]
- Chinmaya Panda, IIT Hyderabad
- Sameer Durgoji, NIT Karnataka
- U. Kumar, L. Sahu and U. Sharma, "Performance evaluation of reversible logic gates," 2016 International Conference on ICT in Business Industry & Government (ICTBIG), 2016, pp. 1-4, doi: 10.1109/ICTBIG.2016.7892693.
- A. K. Rajput, S. Chouhan and M. Pattanaik, "Low Power Boolean Logic Circuits using Reversible Logic Gates," 2019 International Conference on Advances in Computing, Communication and Control (ICAC3), 2019, pp. 1-6, doi: 10.1109/ICAC347590.2019.9036799.
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