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View Code? Open in Web Editor NEW27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting
License: GNU Affero General Public License v3.0
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Q(27) confirmation
An independent confirmation of the result would be great. While Q(26) was confirmed less than two months later by a competing second effort using to Russian supercomputers, it appears more patience is needed this time.
Has your Q(27) solution been confirmed four years later?
Typos
There are a few typos
q27/src/README.md:26: handing ==> handling
q27/src/cpp/DBEntry.hpp:34: wich ==> which | witch
q27/src/cpp/DBEntry.hpp:72: thorugh ==> through
q27/src/cpp/q27db.cpp:286: restictions ==> restrictions
q27/src/java/me/preusser/q27/DiniSolver.java:33: Polynom ==> Polynomial
q27/src/java/me/preusser/q27/UartSolver.java:42: Polynom ==> Polynomial
q27/src/dini/DiniBoard.cpp:20: klass ==> class
q27/src/dini/DiniBoard.cpp:31: klass ==> class
q27/src/dini/DiniBoard.cpp:42: klass ==> class
q27/src/vhdl/PoC/common/vectors.vhdl:87: dimmension ==> dimension
q27/src/vhdl/PoC/common/vectors.vhdl:88: dimmension ==> dimension
q27/src/vhdl/PoC/common/vectors.vhdl:779: dimmension ==> dimension
q27/src/vhdl/PoC/common/strings.vhdl:670: hierachy ==> hierarchy
q27/src/vhdl/PoC/common/strings.vhdl:732: comparisions ==> comparisons
q27/src/vhdl/PoC/common/physical.vhdl:856: achived ==> archived
q27/src/vhdl/PoC/fifo/fifo_cc_got_tempput.vhdl:131: Commited ==> Committed
q27/src/vhdl/PoC/sync/sync_Bits.vhdl:16: choosen ==> chosen
q27/src/vhdl/queens/expand_blocking.vhdl:54: Indeces ==> Indexes
q27/src/vhdl/top/dnk7_f5/dnk7_queens1.vhdl:347: Ouput ==> Output
q27/src/vhdl/top/dnk7_f5/dnk7_queens0.vhdl:87: Adress ==> Address
q27/src/vhdl/top/dnk7_f5/dnk7_queens0.vhdl:636: Ouput ==> Output
q27/src/vhdl/top/dnk7_f5/dnk7_queens0.vhdl:669: Ouput ==> Output
q27/src/vhdl/top/dnk7_f5/dini/fifo/fifo_checksum.v:43: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/fifo/fifo_addr.v:319: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/fifo/fifo_async_blk_reg.v:90: useable ==> usable
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:539: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:540: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:541: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:542: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:543: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:544: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:545: dont ==> don't, do not
q27/src/vhdl/top/dnk7_f5/dini/pcie/pcie_dma/user_fpga/pcie_interface.v:546: dont ==> don't, do not
q27/src/vhdl/top/xilinx/sdrc_queens_master.vhdl:21: Parametes ==> Parameters
q27/src/vhdl/top/xilinx/sdrc_queens_master.vhdl:330: Ouput ==> Output
q27/src/vhdl/top/xilinx/sdrc_queens_master.vhdl:363: Ouput ==> Output
q27/src/vhdl/top/xilinx/sdrc_queens_slave.vhdl:358: Ouput ==> Output
string.vhdl, Value := resize(slv, Value'length); Error expected type std_logic_vector
want to use function raw_format_slv_hexfrom string.vhdl
Vivado editor give error on line 359 about the following
Value := resize(slv, Value'length);
Error message is
[Synth 8-2778] type error near resize ; expected type std_logic_vector
How to fix ? Is it specific to Vivado ?
Brahim @ DCT :: DSI
Execution Time
Hi Thomas, could you include any information about the total execution time that it took to get the Q27 solutions?
For Q26, you reported 8 months and I counted 368 solvers.
For Q27 I count 2747 solvers, but I guess what is the execution time ? an approximate number (months, years (?) ) would be ok.
BR.
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