priyankartalukdar / mytest Goto Github PK

This is a complete simulation optimization framework created as part of my research work. The tool solves the low power pipelining problem. The tool is based on : 

sathi.py : A heursitic approach to large scale circuit optimization.
solver/subsolver.py : Geometric Programming formulation based mathematical modeling using cvx-opt.


Abstract: 
Pipelining of combinational circuits with power, area and clock frequency constraints is a very useful way to increase operational speed of circuits. We solve the pipelining problem as a special case of retiming problem combining the effects of area-timing-power trade-off using gate sizing. For design constraints of area, power and gate sizing range, we give heuristic methods to attain pipelining close to optimal power aware minimum latency pipelined circuit. In this paper we formulate this problem as a Mixed Integer Non Linear Programming (MINLP) problem and we provide two heuristic methods to obtain good solutions. The first method is sensitivity based approach which gives good solution to circuits with large number of gates. The second method uses geometric programming method which is slower on large circuits, but works well for smaller designs. The two algorithms are tested on ISCAS-85 benchmark and circuits generated by our tool and compared for speed and efficiency. We study the varying impact of supply, threshold voltage and logic depth per pipeline stage on pipelining efficiency in terms of latency and total power consumption.