progranism / open-source-fpga-bitcoin-miner Goto Github PK

I'm working with the supplied script and getting 100% rejection rate, any suggestions? BTC to anyone who helps me get the script working.

I'm new to FPGA programming, and I want to try this project out.

Seem like those codes are not very "device specific" so where should I change?
FYI, I'm using DE0 Nano SoC. It has a Cyclone V SE 5CSEMA4U23C6N on board.

Thanks.

Hello, your project are great!!!

Could you please answer if it will be run on
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/cyclone-10-lp-evaluation-kit.html
And what hashrate will be?

Thanks in advance.

fpgaminer_top.v

you have a long compare each time round the loop

// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)

modify nonce2 to make it 1 bit longer, then change the above to a test for a single high end bit, this will take the logic from a 32 bit compare chain to a 1 bit compare chain...
it should push the rate up.

I'm trying to port this firmware to a slightly different FPGA development board. It's the DE2, the predecessor to the DE2-115 already supported. It has the Cyclone II EP2C35F672C6 FPGA. Starting from the existing DE2_115 unoptimized version, I have the project building successfully for this board and creating the bitstream. Running the mine.tcl script, I can see it find both the USB Blaster JTAG and the FPGA behind it:

Looking for and preparing FPGAs...

0. USB-Blaster [USB-0]
   @1: EP2C35 (0x020B40DD)

Selecting that board, it rightly claims that it does not having the mining firmware installed. I can program the sof bitstream through the USB Blaster from Quartus and it appears successful, but after that, the JTAG interface is no longer functional. Running mine.tcl finds the blaster, but does not see the FPGA behind it anymore. Attempting to re-flash the firmware also no longer works and I have to power cycle the board to continue on.

My guess is something is not set up with the clock or PLL configuration. My board runs at 50 MHz and it looks like the osc_clk is correctly mapped to PIN_N2 in the project. Any pointers on how to diagnose the issue would be appreciated.

I am using VHDL_Xilinx_Port FPGA but have a problem with miner.py. Here is miner.log (same as terminal output):

Connecting to FPGA... Done
Measuring FPGA performance... Timed out waiting for FPGA to accept work

and it dies. I tried to increase self.fpga.timeout from 1 to 10 or even 100 with the same result.Is there anything else I should try?

Hi,

I have tried to use the pipelined version on my DE0 Board (Cyclone III EP3C16F484. I have a valid .sof file that works with the board (I think), but the miner.bat does not recognize the board, although I have added it to the mine.tcl script. Error message:

ERROR: The specified hardware is not found.

    while executing
"get_insystem_source_probe_instance_info -hardware_name "USB-Blaster \[USB-0\]"
-device_name "@1: EP3C120/EP3C16F484 (0x020F70DD)""
    (procedure "find_instances" line 3)
    invoked from within
"find_instances"
    (file "mine.tcl" line 165)

The changes I have made to the files can be seen in my Fork:

commit: 541ecd3

Greetings, youRFate

Hello All,

I have a xilinx ZCU102 board.

I just have two questions:

1. This project is pretty old. Has there been no update in bitcoin code in last 11 years? I am asking because ethereum code changed quite a lot since its launch. Has bitcoin code been the same? Is this project still valid for current bitcoin?
2. The changes that I need to make in this project build and work on ZCU102 board.
   Not looking for you to do my work. Just want to know the steps/flow of changes I need to make to get it to work on a new board.
   NOTE: Sorry I am new to fpga development board.
   Does anyone have a project build for zcu102 board or other latest xilins boards??

Thanks,
Kapoor7997

Hi @progranism,

I am trying to run the given program on DE2-115 for the first time.

FPGA got programed successfully, but the mining script is giving the following error. Could you look into it and let me know what could the reason for this error.

I am implementing this code on Xilinx FPGA for learning purposes but there is a small issue if you can help me.

always @ (posedge clk)
	begin
		if (!feedback)
		begin
		
			tx_hash[`IDX(0)] <= rx_state[`IDX(0)] + HASHERS[64/LOOP-6'd1].state[`IDX(0)];
			tx_hash[`IDX(1)] <= rx_state[`IDX(1)] + HASHERS[64/LOOP-6'd1].state[`IDX(1)];
			tx_hash[`IDX(2)] <= rx_state[`IDX(2)] + HASHERS[64/LOOP-6'd1].state[`IDX(2)];
			tx_hash[`IDX(3)] <= rx_state[`IDX(3)] + HASHERS[64/LOOP-6'd1].state[`IDX(3)];
			tx_hash[`IDX(4)] <= rx_state[`IDX(4)] + HASHERS[64/LOOP-6'd1].state[`IDX(4)];
			tx_hash[`IDX(5)] <= rx_state[`IDX(5)] + HASHERS[64/LOOP-6'd1].state[`IDX(5)];
			tx_hash[`IDX(6)] <= rx_state[`IDX(6)] + HASHERS[64/LOOP-6'd1].state[`IDX(6)];
			tx_hash[`IDX(7)] <= rx_state[`IDX(7)] + HASHERS[64/LOOP-6'd1].state[`IDX(7)];
		
		end
	end

IDX is not defined that's the error which i am facing. Is it just a variable ? or what? Thanks

Playing about with the current pyton code for submitting jobs, seems unstable once the number of boards is scaled up.

Really the RS232 interface could do with a BFGminer plugin.

can anyone guide me that what Intel Quartus compiler should i have to use to implement this bit miner code? or any procedure file which can help me to build all projects. Thanks

In src folder of the project there is no Verilog module / component altsource_probe_component.

I want to contribute in translation to Filipino

I am not able to find module defination for following instances

e0  e0_blk  (rx_state[`IDX(0)], e0_w);
e1  e1_blk  (rx_state[`IDX(4)], e1_w);
ch  ch_blk  (rx_state[`IDX(4)], rx_state[`IDX(5)], rx_state[`IDX(6)], ch_w);
maj maj_blk (rx_state[`IDX(0)], rx_state[`IDX(1)], rx_state[`IDX(2)], maj_w);
s0  s0_blk  (rx_w1, s0_w);
s1  s1_blk  (rx_w14, s1_w);

Above are the instance present in sha256_transform.v

https://hackaday.io/project/159108-ulx3s-powerful-ecp5-board-for-open-source-fpga

Hi there.

Working on a DE0-nano board and using the HDL from https://github.com/kramble/DE0-Nano-BitCoin-Miner but I am using the script here to mine, like the page over there says.

It looks like I've got everything working and set up correctly. However, when I go to run the script, a message in the terminal says that new work cannot be fetched because the "stratum+tcp" protocol is not supported.

I'm doing this for fun, not for profit (not really worth it anymore anyway), but I'd really like this to work if I can.

Any advice or links to head to online to get this little guy running? Thanks!

Could You please add the files in projects/DE2_115_NIOS_Ethernet_Test/src/cpu

Hi
How do I load it in Quartus, compile it and upload it to my MKR Vidor 4000 (Intel Cyclone 10 LP) without a USB Blaster?
Regards

I have a papilio duo laying around and was interested in turning it into a miner. I was hoping for some guidance as to what changes i will need to make and such. Thanks

I am not able to find module defination for following instances

altshift_taps # (.number_of_taps(1), .tap_distance(LENGTH), .width(32)) shifttaps

I've tried to synthesize the VHDL-Core for a Xilinx XC3S700A , but ISE hangs now for over 45 minutes now in "Advanced HDL Synthesis". Is this supposed to be normal?

I can't connect to the pool. My hash rate shows 0.02 MH/s (~0.00 MH/s) without any errors on screen. My board is DE2i-150 and my pool is slushpool.

as a newer,please tell me what is the 'your password here'

When I try to run program-fpga-board.bat

I got error message such as :
System cannot find the path specified.

Can you give me some instructions on what to do? Should I put the files in a different folder/

Thank you.

I´m trying to connect to Slushpool using this Miner loaded on a DE0 Nano SoC. Even though the miner connects to the stratum proxy and the Slushpool page creates a new worker if I run the miner specifying the worker on the "config" file , the page show me the worker as "offline". It doesn´t show me any actual hashrate, too. In the miner window, after it begins accepting jobs, the hashrate is about ~2100 MH/s. I know it´s nothing compared to the hashrates nowadays, but shouldn´t the page at least show me the hashrate, or my worker active? Thanks.

Does anyone has the OS Miner already running on this CV SoC Board?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/products/devkits/altera/documents/qs_alt_cvsoc_devkit.pdf

First of all: Thank you for maintaining this project.

I used a Terasic Development board in first semester but didn't learn Verilog or Altera HDL. Some minor VHDL knowledge is there, but it's not really enough for such a project.

Is there a easy way to convert the project to run on a Altera FLEX 10K20 FPGA, mounted on a UP1 Development Board? I know, Hashrate will be poor.

best regards,

Sascha

Hey, i have never use a FPGA borad, i will try the prodject on a smalelr device to understund more and mabye in the futurce buy and bigger board.

I looked up Altera MAX II EPM240. and under stund that is an smal one. but is it easy to get this project to work with that device?

http://www.ebay.com/itm/Altera-MAX-II-EPM240-Core-Board-FPGA-CPLD-Development-Kits-JTAG-USB-Blaster-/330813186044?pt=LH_DefaultDomain_0&hash=item4d06009ffc

http://www.altera.com/devices/cpld/max2/overview/mx2-overview.html

BR Patrik

Has anyone run simulation on this?
The simulation prints hash2 values. How do I compare them with the golden values, such as those produced by C models in:

https://github.com/B-Con/crypto-algorithms

Thanks.