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axi_mem_if's Issues

Width mismatches

I'm getting width mismatch warnings on the last warp_address assignments

    if (len == 4'b1)
        warp_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:1+LOG_NR_BYTES];
    else if (len == 4'b11)
        warp_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:2+LOG_NR_BYTES];
    else if (len == 4'b111)
        warp_address[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:2+LOG_NR_BYTES];
    else if (len == 4'b1111)
        warp_address[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-3:4+LOG_NR_BYTES];

I haven't dug into the code to figure out how it all works, but looking at the first ones that don't have warnings, I wonder if it should just be

    else if (len == 4'b111)
        warp_address[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:3+LOG_NR_BYTES];
    else if (len == 4'b1111)
        warp_address[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES] = unaligned_address[AXI_ADDR_WIDTH-1:4+LOG_NR_BYTES];

WLAST is ignored when FSM is in WAIT_WVALID

There seems to be an issue in the WAIT_WVALID state:

axi_mem_if/src/axi2mem.sv

Lines 160 to 171 in 4d05b1f

WAIT_WVALID: begin
slave.w_ready = 1'b1;
addr_o = ax_req_q.addr;
// we can now make our first request
if (slave.w_valid) begin
req_o = 1'b1;
we_o = 1'b1;
state_d = (slave.w_last) ? SEND_B : WRITE;
cnt_d = 1;
state_d = WRITE;
end
end

Once in this state, the FSM jumps unconditionally to WRITE, regardless of the value of w_last. Under certain conditions, this prevents the b_valid signal to be sent, which might lead to a deadlock.

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