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This project's goal is to create a SystemVerilog silicon independent TCP/IP implementation.

• Functional TCP/IP stack capable of listening and connecting;
• SACK-capable (tx and rx);
• ARP table and request/reply;
• ICMP reply (ping);
• DHCP client;
• 1-Gbit RGMII MAC (8-bit datapath).

• No compliance to RFC;
• Low tx and rx buffer sizes (only on-chip RAM used);
• Static RTO;
• Only 1 connection per instance;
• Limited simulation and hardware tests.

• src. Source files for synthesis;
• ver. Files related to verification
• tb. Testbench location;
• hw. Hardware examples;
• hdl_generics. Submodule containing generic HDL components

Physically, a 10/100/1000 Mbit GMII/RGMII capable PHY should be connected to the FPGA. The top-level entity to be instantiated by user is eth_vlg described in eth_vlg.sv. The ports provided are used to configure and control eth_vlg as well as to send and receive data.

User data stream connections for TCP and UDP are provided via tcp_xxx and udp_xxx respectively. The control and status lines for DHCP and TCP are also there. Please note that TCP and UDP become avaliable after DHCP has either succeeded or failed to obtain an IP address.

The design is clocked by two (possibly asynchronous) 125MHz clocks:

• Receive clock is provided by PHY itself as part of RGMII/GMII interface: phy_rx_clk.
• Internal logic and transmit clock is provided by user via clk port with corresponding synchronous rst. Same clock as phy_rx_clk may be used.

Any clock-to-data skew is possible as the PLL in receive path allows for arbitrary phase shift (see example in hw folder). Receive clock provided by PHY is used only as receive PLL reference clock. All logic is including CDC is clocked by the receive PLL's output. The PLL is used to align data to clock for correct timing. This clock drives the input DDR I/O primitives used for RGMII and the write port of CDC FIFO.

Clock domain crossing is handled by mac_vlg_cdc. GMII signals from DDR input primitives are written to CDC FIFO containing true dual-port RAM in receive clock domain. These signals are then read from the FIFO to clk domain. The readout starts a few ticks after empty flag of the FIFO goes low and stops when empty goes high again. This delay is introduced to make sure that there is always at least one unread byte in FIFO (as seen from read side) while the packet is being simultaneously written and read. This is important as subsequent receive logic is expecting uninterrupted data validity val signal during reception of a single packet. While this does not pose a problem if read clock is slower then write clock or if they are coherent, interruptions in val may occur if read clock is faster then write clock especially with longer packets.

The same clock clk used for clocking logic is fed to transmit clock PLL that geenrates phy_gtx_clk with correct phase shift in order to meet PHY's timing requirements.Reference clock for the tx PLL is supplied externally from outside the FPGA. If no 125MHz clocks are present on the PCB, one can generate two 125MHz clocks: one for internal use and the other for phy_gtx_clk and defined correct phase shift between these clocks.

Sample constaints.sdc is supplied with Cyclone 10 LP Evaluation Kit example project: hw/c10lp_eval_kit/src/. Firstly, PLL clocks are defined with desired phase shifts. For Intel FPGAs it's important to note that actual synthesys parameters of PLLs are set in rgmii_rx_pll.v and rgmii_rx_pll.v located in hw/c10lp_eval_kit/ip/. The altpll_component.clk0_phase_shift sets phase shift in ns units (unlike degrees in .sdc). A warning will appear in Quartus if these parameters do not match. Receive and transmit clock domains are separated by means of set_clock_groups -asynchronous. The rx constraints are described using virtual clock. It may be necessary to empirically set the rx and tx PLL's phase shift to achieve stable data latching and timing requrements of PHY.

   ╔══════╗     ╔═══════════════════════════════════════╗
   ║      ║     ║               ╔═════╗ ╔════╗          ║
   ║   ┌──╫─dat─╫────────►╔═══╗ ║dpram║ ║sync║ ╔═══════╗║
   ║   │rx╟     ║╔═══╗    ║ddr╟─►w   r╟─►    ╟─► core  ║║
   ║   └──╫─clk─╫╢pll╟─┬─►╚═══╝ ╚▲═══▲╝ ╚═══▲╝ ║ logic ║║
   ║PHY   ╢     ║╚═══╝ └───clk───┘   └─clk──┤  ║       ║║
   ║      ╢     ║         ╔═══╗◄─────dat────┼──║       ║║
   ║   ┌──╢◄dat─╫─────────╢ddr║             │  ║       ║║
   ║   │tx║     ║╔═══╗    ╚═══╝◄┐           │  ╚═══▲═══╝║ ╔════╗
   ║   └──╢◄clk─╫╢pll╟──────────┴────clk────┴──────┴────╫─╢xtal║
   ║      ║     ║╚═══╝                                  ║ ╚════╝
   ╚══════╝     ╚═══════════════════════════════════════╝

Sample project is provided targeting Cyclone 10 LP EvaluationpKit. The project implements ESG protocol over TCP/IP. The logic is connected to onboard LEDs D6-D9. Default IP is 192.168.1.213 if no DHCP server is on LAN. TCP port is 1000. After establishing a TCP connection with PuTTY or other tools, type:

`ver;

You should get a string response containing version and build date. Note: be sure to check Raw in connection type field if using PuTTY.

The top-level parametaers provide flexibility in configuring the core.

Table 1:

The top-level ports provide real-time connection control and monitoring.

Table 2:

Simple testbench is provided to verify functionality. Run modelsim.bat inside tb folder. (modelsim.exe location should be in PATH) 2 modules are instantiated, for client and server. After DHCP sequence and ARP, 3-way handshake is performed and TCP data is streamed in both directions.

The code was compiled with for

• Cyclone V (5CEBA5) -8 speed grade with Texas Instruments DP83867IR PHY (Quartus 17.1) on a custom PCB.
• Cyclone 10 LP -8 speed grade with RTL8211 PHY (Quartus 18.0) using QMTech Cyclone 10LP development kit. Both failed timing, although worked as expected. Changing speed grade to -7 fixed timing.

You can manually specify target FPGA family, part and flash memory used in create_prj.tcl.

set FamilyDev "Cyclone V"
set PartDev "5CEBA5F23C8"
set MemDev "EPCS64"
set FlashLoadDev "5CEBA5"

The pins are modified in pins.tcl.

To compile an example project, run complete_flow.bat. (quartus.exe location should be in PATH). To add code to your desired project