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qsnns

Quantization-aware training with spiking neural networks

quartz

quartz_loihi

rainbow-memory

Official pytorch implementation of Rainbow Memory (CVPR 2021)

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

ramulator-pim

A fast and flexible simulation infrastructure for exploring general-purpose processing-in-memory (PIM) architectures. Ramulator-PIM combines a widely-used simulator for out-of-order and in-order processors (ZSim) with Ramulator, a DRAM simulator with memory models for DDRx, LPDDRx, GDDRx, WIOx, HBMx, and HMCx. Ramulator is described in the IEEE CAL 2015 paper by Kim et al. at https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf Ramulator-PIM is used in the DAC 2019 paper by Singh et al. at https://people.inf.ethz.ch/omutlu/pub/NAPEL-near-memory-computing-performance-prediction-via-ML_dac19.pdf

ramulator2

Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf

ramulatorsharp

RamulatorSharp is a fast and flexible memory subsystem simulator implemented in C# and it can easily run on Linux, OS X, and Windows. The simulator contains the implementation of the Low-Cost Inter-Linked Subarrays (HPCA 2016) and ChargeCache (HPCA 2016) in addition to other features present in the C++ version of Ramulator: https://users.ece.cmu.edu/~omutlu/pub/lisa-dram_hpca16.pdf https://users.ece.cmu.edu/~omutlu/pub/chargecache_low-latency-dram_hpca16.pdf

ranger

rate_vs_direct_snn

[ICASSP2022] RATE CODING OR DIRECT CODING: WHICH ONE IS BETTER FOR ACCURATE, ROBUST, and ENERGY-EFFICIENT SPIKING NEURAL NETWORKS

really-awesome-gan

A list of papers on Generative Adversarial (Neural) Networks

reckon

ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.

reference

Reference implementations of MLPerf benchmarks

ripes

A graphical 5-stage RISC-V pipeline simulator & assembly editor

rram_compiler

This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College London

s2n2

s4nn

Temporal backpropagation for spiking neural networks with one spike per neuron, by S. R. Kheradpisheh and T. Masquelier, International Journal of Neural Systems (2020), doi: 10.1142/S0129065720500276

sata_sim

scale-sim

scarab

Joint HPS and ETH Repository to work towards open sourcing Scarab and Ramulator

sdnn_python

semanticsegmentfpga

shiftaddnet

[NeurIPS 2020] ShiftAddNet: A Hardware-Inspired Deep Network

sigma

RTL implementation of Flex-DPE.

siliconcompiler

A modular build system for hardware

sinabs

A deep learning library for spiking neural networks which is based on PyTorch, focuses on fast training and supports inference on neuromorphic hardware.

sinabs-exodus

Plugin for Sinabs, implementing the EXODUS algorithm for training SNNs efficiently with BPTT

slayerpytorch

PyTorch implementation of SLAYER for training Spiking Neural Networks

snasnet

Neural Architecture Search for Spiking Neural Networks, ECCV2022

snn-conversion