ravenslofty / 74xx-liberty Goto Github PK

The makefile in the sim directory can not create counter.vcd

make: *** No rule to make target `counter.vcd', needed by `all'.  Stop.

Would be nice to add some text so random internet wanderers know what they are looking at and how to use it.

I'm thinking I should write down my learnings on how to write code that synthesizes to a small chip count.

Did you forget to commit this?

Today I was experimenting with using this project with the experimental GHDL Yosys plugin: https://github.com/tgingold/ghdlsynth-beta

I ran into issues because the synth script has hardcoded paths relative to the current directory, not the scripts directory, so it only works from subfolders of this repo. So that doesn't really work when you want to use it in another project. (Like a TTL dual stack CPU :)

@daveshah1 mentioned that there is a TCL API, so it should be possible to encode the paths relative to the script file with some trickery. help tcl tells me it can import the yosys commands into the TCL shell, so it just needs a few lines to make the correct paths.

While I'm at it I might also add VHDL support to the Makefile, but that stuff is very experimental and requires a lot of extra setup. So maybe I'll just keep that for my own entertainment until it's a bit more stable and complete. (I plan to contribute to GHDL a bit over the summer)

When looking at the stat output for VexRiscv you can see two $dff, of the lowercase, pre-synth kind. It appears they originate from the memory_bram rule. Commenting that out gives a $mem item, and uncommenting memory_map gets rid of all the weirdness.

Probably the solution is to move the bram step to before synth so that the output registers it creates are synthesized. But maybe there is a reason it's all the way at the end?

Currently we only generate $add cells based on the 74AC283, but Yosys has a bunch of other things that we could look into.

Summary of the discussion so far as I understand it:

• 74181 does not match $alu but could in theory be hardwired for specific functions
• 74181 is not in production it seems, so hard to get
• The 74182 should make a good $lcu
• A 7485 comparison pass was tried, but slightly worse than plain logic
• But variables take over twice as much logic, so maybe worth it
• We could generate $sub with an inverter and adder
• Yosys could maybe figure this out by itself, but experimentation shows it just generates plain logic

The makefile in the kicad directory references a file called boneless.net

make: *** No rule to make target `boneless.net', needed by `all'.  Stop.

Maybe the file was forgotten to be checked in to git?

The following code produces zero cells on any commit I've tried, so I think it's not something that broke with any recent changes. Changing the multiplication to an addition or making it synchronous reset makes the problem go away.

I tracked the compilation process, and it gets optimized away here: https://github.com/ZirconiumX/74xx-liberty/blob/ca39c8333b0fb642837659dca925dfc37913877a/synth_74.ys#L20

Removing the opt and the opt below it, it produces some output, but simulating it gives incorrect results. I stared at the incorrect output for a while, but it's hard to make sense of the ball of NAND and XOR gates that is supposedly a multiplier.

module counter (
  input rst,
  input clk,
  output led
    
);

    /* reg */
    reg [7:0] counter = 0;
    
    /* assign */
    assign led = counter[7];
    
    /* always */
    always @ (posedge clk or negedge rst) begin
      if (!rst) begin
        counter <= 1;
      end else begin
        counter <= counter * 8'd3;
      end
    end

endmodule

I'm attempting to build the pwmled example, but upon running make I get the following error:
make: *** No rule to make target 'pwmled.net'. Stop.

This appears to be because 74series.lib has been renamed to 74ac.lib. Upon copying 74series to 74ac some of the basic examples work (like counter), but pwmled and some of my own code fails with errors like the following:

aled@blackdufous-~/build/74xx-liberty/kicad: KICAD_SYMBOL_DIR=/usr/share/kicad/library/ make pwmled.net
yosys -q -s ../synth_74.ys -p "write_json pwmled.json" ../benchmarks/pwmled.v
python3 generate_netlist.py pwmled.json
Traceback (most recent call last):
  File "generate_netlist.py", line 192, in <module>
    create_chips(chip_types, nets)
  File "generate_netlist.py", line 178, in create_chips
    raise Exception("%s not handled" % typ)
Exception: \74AC86_4x1XOR2 not handled
make: *** [Makefile:9: pwmled.net] Error 1
rm pwmled.json