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To match nextpnr's Arch::getTileBelDimZ

The Cyclone V has 18x18 bit multiplier cells, which Quartus calls cyclonev_mac. We should use them.

Some initial experimentation suggests that, contrary to expectations and the current docs,

TCLK_SEL actually controls the clock/enable for FFT0 and FFB1.
BCLK_SEL actually controls the clock/enable for FFB0 and FFT1.

i.e. the '1' FFs take their clock from the opposite half.

It seems like this behaviour doesn't apply to [TB]SLOAD_EN and [TB]SCLR_DIS. I haven't checked the ACLR selection yet.

The mapping of LAB-wide control signals to DATAIN pnodes doesn't always match the mux names well. This is what I have documented so far, although further experimentation is needed.

ENA0 DATAIN.2
ENA1 DATAIN.3
ENA2 DATAIN.0

clock, when coming from general routing

CLKA DATAIN.0

using CLKB seems to make CLKA use DATAIN.1.

SCLR defaults to DATAIN.3, but it seems like EN0_SEL GIN3 can mux it to DATAIN.1.

SLOAD defaults to DATAIN.1, but it seems like EN1_SEL GIN1 can mux it to DATAIN.2.

See gatecat/nextpnr@6fc050a

TPKREG1, for example, actually seems to configure FFT0. I'm not sure if this is bad naming from Quartus or something Mistral has control over.

Presumably a clock-enable cell?

Hi. I know that it is experimental, but I saw a blinking led several months ago on Twitter (I didn't find it again). I have a DE10-nano and I want to try (as far I remember, the example was in this same board).

Regards,
Rodrigo

Is this format compatible with Cyclone IV?

Hi, we have a couple bin's dumped from the analogue pocket flash chips. Would you like to help inspect them for bitstreams?

env:

ubuntu@10-9-99-245:~/mistral/build$ uname -a
Linux 10-9-99-245 5.4.0-48-generic #52-Ubuntu SMP Thu Sep 10 10:58:49 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
ubuntu@10-9-99-245:~/mistral/build$ cat /etc/issue
Ubuntu 20.04 LTS \n \l

When I make with make VERBOSE=1, I get this

/usr/bin/cmake -S/home/ubuntu/mistral -B/home/ubuntu/mistral/build --check-build-system CMakeFiles/Makefile.cmake 0
/usr/bin/cmake -E cmake_progress_start /home/ubuntu/mistral/build/CMakeFiles /home/ubuntu/mistral/build/CMakeFiles>>/progress.marks
make -f CMakeFiles/Makefile2 all
make[1]: Entering directory '/home/ubuntu/mistral/build'
make -f tools/CMakeFiles/tools.dir/build.make tools/CMakeFiles/tools.dir/depend
make[2]: Entering directory '/home/ubuntu/mistral/build'
cd /home/ubuntu/mistral/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/ubuntu/mistral /home/ubuntu/mistral/tools /home/ubuntu/mistral/build /home/ubuntu/mistral/build/tools /home/ubuntu/mistral/build/tools/CMakeFiles/tools.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/ubuntu/mistral/build'
make -f tools/CMakeFiles/tools.dir/build.make tools/CMakeFiles/tools.dir/build
make[2]: Entering directory '/home/ubuntu/mistral/build'
make[2]: Nothing to be done for 'tools/CMakeFiles/tools.dir/build'.
make[2]: Leaving directory '/home/ubuntu/mistral/build'
[ 4%] Built target tools
make -f generator/CMakeFiles/generator.dir/build.make generator/CMakeFiles/generator.dir/depend
make[2]: Entering directory '/home/ubuntu/mistral/build'
cd /home/ubuntu/mistral/build && /usr/bin/cmake -E cmake_depends "Unix Makefiles" /home/ubuntu/mistral /home/ubuntu/mistral/generator /home/ubuntu/mistral/build /home/ubuntu/mistral/build/generator /home/ubuntu/mistral/build/generator/CMakeFiles/generator.dir/DependInfo.cmake --color=
make[2]: Leaving directory '/home/ubuntu/mistral/build'
make -f generator/CMakeFiles/generator.dir/build.make generator/CMakeFiles/generator.dir/build
make[2]: Entering directory '/home/ubuntu/mistral/build'
make[2]: Nothing to be done for 'generator/CMakeFiles/generator.dir/build'.
make[2]: Leaving directory '/home/ubuntu/mistral/build'
[ 20%] Built target generator
make -f libmistral/CMakeFiles/mistral.dir/build.make libmistral/CMakeFiles/mistral.dir/depend
make[2]: Entering directory '/home/ubuntu/mistral/build'
[ 21%] Generating e50f-r.bin
cd /home/ubuntu/mistral/build/libmistral && ../generator/generator /home/ubuntu/mistral/libmistral/../data e50f /home/ubuntu/mistral/build/libmistral 1
Killed

make[2]: *** [libmistral/CMakeFiles/mistral.dir/build.make:264: libmistral/e50f-r.bin] Error 137
make[2]: Leaving directory '/home/ubuntu/mistral/build'
make[1]: *** [CMakeFiles/Makefile2:211: libmistral/CMakeFiles/mistral.dir/all] Error 2
make[1]: Leaving directory '/home/ubuntu/mistral/build'
make: *** [Makefile:130: all] Error 2

How can I do?

In current state mistral is able to generate bitstream for 5CEFA5F23I7 / 5CEFA5F23C8. Unfortunately, the fpga is unable to run successfully the bitstream to sram and revert to previously loaded bitstream in flash produced by quartus.

When comparing decompiled bitstream between mistral and quartus there are missing CMUXVG and CMUXHG statement at the beginning of each bitstream for 5CEFA5F23I7 by mistral.

Also, when decompiling quartus generated bistream, mistral-cv output this

Source unknown on rnode SCLK.014.000.0015 ( 6, 01)
Source unknown on rnode SCLK.014.000.0020 ( 6, 04)
Source unknown on rnode SCLK.014.000.0025 ( 6, 08)
Source unknown on rnode SCLK.047.000.0005 ( 6, 08)
Source unknown on rnode SCLK.047.000.0009 ( 6, 02)

I have compared decompiled bistream between mistral and quartus for 3 examples here

In summary decompiled bistream generated by mistral begin like this

m 5CEFA5F23C8
o COMPRESSION_DIS 1
o OPT_B ffffff40.adffffff
r SCLK.047.000.0009 SCLKB1.047.001.0055
r SCLK.047.000.0009 SCLKB1.047.002.0054
r SCLK.047.000.0009 SCLKB1.047.003.0055

and decompiled bistream generated by quartus begin like this

m 5CEFA5F23C8
o COMPRESSION_DIS 1
o IDCODE 22
o JTAG_ID 0078fd4b
o OPT_B ffffff40.adffffff
r CMUXVG.028.000.0:CLKOUT SCLK.014.000.0000
r CMUXVG.028.061.0:CLKOUT SCLK.014.000.0001
r CMUXVG.028.000.3:CLKOUT SCLK.014.000.0005
r CMUXVG.028.061.1:CLKOUT SCLK.014.000.0010
r CMUXVG.028.000.1:CLKOUT SCLK.014.000.0012
r CMUXVG.028.061.0:CLKOUT SCLK.014.000.0013
r CMUXVG.028.061.3:CLKOUT SCLK.014.000.0014
r CMUXHG.000.008.0:CLKOUT SCLK.014.000.0022
r CMUXHG.000.008.3:CLKOUT SCLK.047.000.0007
r CMUXHG.000.008.0:CLKOUT SCLK.047.000.0008
r CMUXHG.068.008.3:CLKOUT SCLK.047.000.0010
r CMUXHG.000.008.3:CLKOUT SCLK.047.000.0020
r CMUXVG.028.000.1:CLKOUT SCLK.047.000.0021
r CMUXHG.068.008.2:CLKOUT SCLK.047.000.0024
r CMUXVG.028.000.2:CLKOUT SCLK.047.035.0027
r SCLK.047.035.0027 SCLKB1.047.047.0163
r SCLK.047.035.0027 SCLKB1.047.048.0163

I don't know if I can re-inject those CMUXHG CMUXVG from quartus to mistral, then ajusting numbers like 047.035.0027 for SCLK. Then recompile to rbf and try if it work on fpga.

Other than that, bitstream generated by mistral is very close to quartus.

Let me know if there are experiments I can do to try make mistral working on Cyclone V 5CEFA5F23 device.
Thanks.

Only the Cyclone IVs have M9Ks, I believe.

TEF_SEL actually selects between E0 and F1 (not F0)
BEF_SEL actually selects between E1 and F0 (not F1)

I think the schematic and docs need updating to reflect this...