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adv_debug_sys

Advanced Debug System

align-public

amba_components

Verilog modules that implements various AMBA related interface conversion

antlr2insta

A grammar conversion tool from antlr to instaparse

apb-bridge

An APB bridge and mux generator based on the junctions/Poci chisel code

apitest

Testing a REST API using https://my-json-server.typicode.com/

arduino-lcd-keypad-8digits

An Arduino sketch to be used with an DFRobot LCD/keypad shield for entering a value up o 8 digits

arduino-makefile

Makefile for Arduino sketches. It defines the workflows for compiling code, flashing it to Arduino and even communicating through Serial.

arm-gcc-build

Script to build a custom arm toolchain for embedded developement (Under construction)

arty-cm0-designstart

A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board

async_logic

A collection of asynchronous logic circuits as found in the litterature

autockt

Deep Reinforcement Learning of Analog Circuit Designs

avr32freertos

FreeRTOS port for AVR32 AP7000 (code from SourceForge)

backlog

Python program to compute project backlog

boolean-logic

experimentation with boolean logic and clojure

bsg_fakeram

fakeram generator for use by researchers who do not have access to commercial ram generators

cdargs

Directory bookmarking system - Enhanced cd utilities

cocotb

Coroutine Co-simulation Test Bench

darkriscv

opensouce RISC-V implemented from scratch in one night!

dat0x5-thesis

Automatically exported from code.google.com/p/dat0x5-thesis

devilspie2

Program to use LUA to find windows, and perform actions on them - This project will soon be moved to Gna! - which also includes the google groups that will migrate to a Gna mailinglist. Git services will be moved to gitorious.

diagram-automation

dita-ng

Automatically exported from code.google.com/p/dita-ng

doxymacs

Doxymacs is Doxygen + {X}Emacs.

edn_2015_01_12

A Verilog implementation of the gating circuit described in EDN : http://www.edn.com/design/systems-design/4438302/Circuit-gates-pulse-train-without-truncating

elua-evk1104

eLua Project on GitHub

eqy

Equivalence checking with Yosys

forth

attempt to write a simple Forth interpreter in Python

grammars-v4

Grammars written for ANTLR v4; expectation that the grammars are free of actions.

gridengine

Univa Grid Engine Open Core