rbarzic Goto Github PK

pybind11

Seamless operability between C++11 and Python

pybison

Use Bison directly from Python

pycfg

Experiments using Python code/data structure as configuration files

pycparser

C parser and interpreter written in Python with automatic ctypes interface generation

pyeda

Python EDA

pymata4

A High Performance Python Client For Arduino Firmata

pyspice

Simulate electronic circuit using Python and the Ngspice / Xyce simulators

python-arduino-proto-api-v2

A Python-Arduino-Prototyping-API fork gone wild - Local fork

python_threading_examples

pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

pyverilog-test

Tests for the pyverilog Verilog parser

raspberrypi

My working environment for interacting with my raspberry pi(s)

rbarzic.github.io

RB's website

riscv-formal

RISC-V Formal Verification Framework

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC 5.3.0

riscv-llvm

Fork of the official riscv-llvm to experiment with LLVM

riscv-opcodes

RISC-V Opcodes

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv-torture

RISC-V Torture Test

simd

A playground for various ideas around SIMD

sky130-lite

A lightweight version of the Skywater Open Source PDK (https://github.com/google/skywater-pdk) (to limit disk and bandwith usage)

spice-examples

Examples to demonstrate use of a few open-source schematic editors for analog schematic edition and simulation

swerv-iss

systemc

A collection of SystemCSystemC-AMS examples

training-day

vcdvcd

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line viewer.

verilator

A collection of Verilator examples

verilog_examples

A few verilog examples to help students to start playing with Verilog and the Icarus simulator

verilog_sim_utils

Various verilog files to help writting testbenches

vlsiflow

Experiments with OpenCircuitDesign, NgSpice,...