This is a VHDL simulator made for half year project during 6th semester of computer enginnering of IOE pulchowk.
- Clone the repo and get inside the folder.
git clone --depth=1 https://github.com/rls129/Lizard/`
cd Lizard- Create a virtual env and activate it.
python -m venv .venv
source .venv/bin/activate # OR
.venv/bin/Activate.ps1- Install all dependencies from requirements.txt.
pip install -r requirements.txt - Run the application
python main.py
entity comparator_1bit is
end entity comparator_1bit;
architecture Behavioral of comparator_1bit is
signal b_i : std_logic;
signal a_i : std_logic;
signal B_less_A_o : std_logic;
begin
B_less_A_o <= a_i and (b_i nand b_i);
process is
begin
a_i <= '0';
b_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
wait for 100 ns;
wait;
end process;
end architecture Behavioral;
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