Currently our training materials are in Chinese language. Please check Zh-CN for more contents. Also check our seminar recordings on Bilibili. The English version is coming soon.

The PLCT Lab is a toolchain team focusing on RISC-V related compilers, emulators, and language virtual machines. It is part of Intelligence Software Research Center (ISRC), which is part of Institute of Software, Chinese Academy of Sciences (ISCAS).

The PLCT Lab is providing RISC-V related skill training, including:

• Write LLVM Backend for RISC-V custom extensions.
• Optimize toolchain for specific CPUs and specific work load.
• Add new CPU or Machine/SoC emulations in QEMU.
• Extend Spike Emulator for custom purpose.

By joining the training program, you could get involved with the latest feature developing among mulitple open source porjects. For example:

• RISC-V Vector Extension in LLVM upstream.
• XuanTie C910 LLVM toolchain development and support.
• Neclei N300 Series SoC and other new SoCsupport in QEMU.
• New feature implementations for Spike emulator.
• Code size and Performance evaluations for RISC-V toolchains.

The Training Program is still in the early development stage. We welcome college students and anyone who is interested in RISC-V software ecosystem to join the program as pilot, work together to improve the project.

Currently the training materials are mainly in Simplified Chinese language. We are working on translating the materials in to English and possibily other languages. Volunteers are welcome!

Contact: wuwei2016[at]iscas.ac.cn