A general slow DDR3 interface.
Very little resource consumption.
Suits for all FPGAs with 1.5V IO voltage.

• Designed to run at DDR-100. (The system freqency is 100MHz and DDR clock frequency is 50MHz)
  DDR-50? That's OK.
  DDR-10? OK, but refresh takes too much clocks.
  DDR-200? Depends on the hardware and the FPGA.
  DDR-400? It may not work. Whatever, take a shot.
  When changing the clock frequency, please modify the clkFreq in the slowDDR3Cfg and recompile it.
• Designed to work with LVCMOS IO
  Only has LVCMOSs? It can work.
• Very low resource consumption
  Wish to attach a DDR3 module to a CPLD? Try it.
• Write in SpinalHDL
  Future is coming.

• slowDDR3.scala
  The SpinalHDL design file.
  Compile it to get the output verilog file.
• slowDDR3.v
  Pre-compiled verilog file.
  Designed to run at 100MHz with a 128Mx16b DDR3 chip.
• tb.v
  Testbench file.
  A DDR3 model is required to do the simulation.
  You may find it at Micron's website.
  DDR3 Model

The burst feature is not implemented yet, so multi read/write will not be faster than single.
The burst may increase the r/w speed to 3x or 4x.

• Single Write
  
• Multi Write
  
• Single Read
  
• Multi Read
  

If Write and Read are issued at the same time, only write will be executed.
You don't need to care about the refresh.

To simulate the design, you need to do some modifications to the model file.

1. change the type of the ddr3.v to ddr3.sv (system verilog)

2. define the size in ddr3.sv
   I use the den2048Mb

   `define den2048Mb
   

3. define MAX_MEM in ddr3.sv

   `define MAX_MEM  
   

4. comment this line in ddr3.sv

   // if (dll_en) init_step = init_step + 1;  
   

5. add a line under it

   init_step = init_step + 1;  
   

6. comment these 2 lines in ddr3.sv

   // if (tck_avg - TCK_MAX >= 1.0)   
   // $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);  
   

7. you are good to go.