russdill / bch_verilog Goto Github PK
View Code? Open in Web Editor NEWVerilog based BCH encoder/decoder
License: Other
Verilog based BCH encoder/decoder
License: Other
Hello, thank you very much for your generous sharing. I would like to know more information about bch. Have you published any literature ? If yes, could you tell me the name of the document?
I ran into this issue when running VCS on the bch_decoder.v. The code uses wire "key_ready" on line 111 but it is declared below that point. Because of that, VCS spits out this error:
Error-[IND] Identifier not declared
bch_decoder.v, 111
Identifier 'key_ready' has not been declared yet. If this error is not
expected, please check if you have set `default_nettype to none.
I've moved the key_ready wire declaration to another spot above line 111 and that solves the issue.
Hi,
First of all thank you for making this great project.
One thing that I have problem with is the difference between the output of bch encoder for BCH(127,71) from MATLAB comm.BCHEncoder even if generator polynomials are the same.
I checked the ENC parameter and it's the same as "genpoly(127,71)" function from MATLAB.
But when I input the same data to both "bch_encode" and MATLAB function i get different encoded data. Actually the difference is only in the second part of data not the original part of data.
Can you please tell me why ?
Thanks
Is there any detection of un-correctable errors when you have more errors than t?
What is the correct procedure to run Makefile.xilinx?
Whenever I try to run:
make -f Makefile.xilinx
I obtain
make: Nothing to be done for 'all'
Note
Successfully compiled Icarus Makefile and ran and visualised the simulation data.
Details
Xilinx ISE 14.7 installed and path environment setup correctly.
OS: Redhat 6.10
Hello, thank you for sharing. I'm a graduate student from Wenzhou University. In order to create a project, I encountered some problems when importing the design resources you shared. The problem is as follows: when importing xilinx_ decoder(one file from your shared files), you will be asked to add "u_ pipeline:xil_ defaultlib.pipeline" this file,but I did not find this file in the folder you shared.Besides,when you add the file"bch_syndrome(one file in you BCH files)", you will be asked to add other files that do not exist in your file in the sub file folder. The development platform I use is vivado 2019.3 .
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