Reimplement `r0`, since it is deprecated about riscv-rt HOT 7 CLOSED

Thanks for opening this issue! I'll take a look. Of course, PRs are more than welcome :)

from riscv-rt.

I’ll have a look at this. Is there a preference for a separate crate again or should it just become a part of the riscv-rt crate?

from riscv-rt.

I prefer to reduce the number of dependencies, but if you find a handy crate that eases the work, then use it.

If I were you, I'd implement it in assembly.

from riscv-rt.

The conclusion when we deprecated r0 was that this can only soundly be implemented in assembly; cortex-m-rt does so here. I think it's best put into your existing startup routine (here).

from riscv-rt.

I see you feature-gate the RAM initialization. Would you recommend us to do the same for riscv-rt?

from riscv-rt.

We can get some inspiration from the esp-hal folks: https://github.com/esp-rs/esp-hal/blob/eeb2d1db6f8ffd250b212bd1bebaddc83d0ea8b0/esp-riscv-rt/src/lib.rs#L294C8-L294C8

from riscv-rt.

I see you feature-gate the RAM initialization. Would you recommend us to do the same for riscv-rt?

That was a later addition from users with MCUs that have things like ECC RAM where you have to write to the entire RAM at startup to initialise the memory controller; usually it's enough to just initialise the .data and .bss sections and leave unused RAM alone. Since there's a startup time cost, it made sense to feature-gate this just for users who need it.

I think you could reasonably support the same feature, but just doing .data and .bss is enough for almost all use cases.

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