Comments (3)
What board/core are you using?
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Is there a linker script that I need? What's causing this?
Yes, you need to pass the linker script name as well as a script with memory definitions in .cargo/config:
https://github.com/riscv-rust/longan-nano/blob/master/.cargo/config
link.x
is provided by riscv-rt, but memory.x
is usually provided by user or one of the chip support crates.
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Thanks! It worked!
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Related Issues (20)
- Support for lld HOT 2
- Build on stable
- rust produces a 2.1G executable HOT 7
- build using -mcmodel = medany HOT 18
- Implement multi-core support
- Bizarre warning behavior around #[entry] macro and `&mut FnMut`
- LiteX/VexRiscv support HOT 4
- Execution start address varies. HOT 3
- Update r0 to 1.0 HOT 1
- Relocation R_RISCV_ALIGN linker error
- ELF output contains lots of zero data: linker script issue? HOT 4
- RAM init code violates pointer provenance and aliasing rules HOT 1
- Migration to GitHub Actions HOT 1
- sp may not be aligned to 16 bytes
- New crates.io release HOT 4
- Accessing parameters passed in register by the previous boot stage HOT 8
- Doesn't compile with the latest nightly toolchain. HOT 4
- Reimplement `r0`, since it is deprecated HOT 7
- asm: Startup code traps into an illegal instruction
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