Dev	Role	Donate
Mike Taylor	Verilog Code
Jorgen Bilander	PCB Design

🔴 This project is still a work in progress and the code and hardware design is likely to change. this is why there are no instructions on how to build or program the board yet.

This project is an exercise in reverse engineering the Commodore SDMAC 390537 as found in the Amiga 3000

This project was started with nothing more that the descriptions of the SDMAC operations and from the Amiga 3000T Service manual, the WD33c93 Datasheets and some source code from the Amiga 3000 Linux scsi drivers.

Since then Partial schmatics surfaced with some pages missing. I've done my best to add the missing pages back and the can be found here SDMAC_Rev4.pdf

To collate togethe the technical details of the SDMAC a markdown document has been created and is linked here This will be updated with timing diagrams, state diagrams schmatic fragments as appropriate.

The FIFO is implmented with an 8 x 32 bit long word buffer, each long word can be loaded one byte at a time, one word at a time (high or low) or all at once. This is controled by the Byte Pointer and the write strobe sub circuit in within the FIFO. Reading from the FIFO is asynchronous and the longword pointed to by the read (Next Out) pointer is always present on the output data bus of the FIFO.

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Details here

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When ordering from JLCPCB select:

Specify Layer Sequence: Yes

L1(Top layer):    F_Cu.gbr
L2(Inner layer1): GND_Cu.gbr
L3(Inner layer2): VCC_Cu.gbr
L4(Bottom layer): B_Cu.gbr

Remove Order Number:

Specify a location

This will notify JLC where to put the order number, they will replace the "JLCJLCJLCJLC" silkscreen label.

Please click here for the Interactive BOM.

Below are the VCD files output by the cocotb tests. these can be used to help verify the verilog code.

Thankyou to all the people who have helped with this project especially:

• Stefan Skotte aka Screemo For the long term loan of a REV 2 SDMAC.
• Andy aka trixster1979 For the long term loan of a REV 4 SDMAC.
• Matt Harlum Liv2 for checking over the my code and interpretation of the FSM schematics.
• Chris Hooper aka CDH For providing various adaptor PCBs and breakout boards, also for writing the SDMAC test program.
• Jorgen Bilander For adapting the ReAgnus design to suit the SDMAC, and also for crating the ReSDMAC-devboard
• Stephen Leary AKA Terriblefire For publishing the verilog code for his projects and inspiring me to learn verilog and take on this project way back in 2021

others that have helped out with words of encouragement and general support.

• John Hertell aka Chucky
• Wrangler
• shanshe
• Stefan Reinauer

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.