custom-processor-for-image-down-sampling's Introduction

Custom-processor-for-image-down-sampling

This repository contains a custom processor and an UART transceiver build using Verilog for the task of image downsampling

Refer the report for more information

Required Software

MATLAB

Quartus

Hardware

Altera DE2-115 development board

How to use

Write the code using the instructions in the ISA

Convert it to the machine instructions using the given compiler

Save it to the instruction memory using Quartus software

Send the image using the matlab code and wait till the recieving is complete

Performance

It takes around 2 minuts for the transmission

less than 1 second for the downsampling

ability to downsample maximum of 256x256x3 image

following diagrams shows the architecture, state diagram and datapath of the processor

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