This repository provides a project template for tesing new verilog (and system verilog) projects. Open a terminal and run:
make TOP=first_counter_tb
This will launch a Vivado simulation for first_counter_tb
in batch mode, and will dump the waveform in top_sim.vcd
. The test-outputs
directory will also be created containing all other generated files.
src
: The application and test source filesmain
: Application sourceshdl
: Core user verilog and system verilog filesresources
: Other files and scripts (including third party resources)
test
: Test sourceshdl
: Core user verilog and system verilog testbench filesresources
: Other simulation files and scripts