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Design of serial parity detector, continues stream of bit are fed via synchronism of clock. Even number of 1 are indicated by "0" and Odd number of bits are indicated by "0". Its an example of Moore Machine.

License: GNU General Public License v3.0

Pascal 2.01% Batchfile 17.68% Verilog 21.61% Tcl 3.19% C 32.77% HTML 22.74%

parity_detector_verilog's Introduction

Hello Hello , I'm Shubham! 👋🏻

  • ⚡ I am Shubham Rajput, student at NIT Delhi studying MTech ECE.
  • 🎓 I mostly do Machine Learning development but being a Mechatronics enthusiast I am constantly exploring other fields too.
  • 🤖 These days I am learning OCR (Optical Character Recognition) in Python
  • 😋 Besides programming, I love watching Anime and watching different TV series.


Shubham's Stats

📊 Weekly development breakdown

Python       ████████████████▓░░░   90.20 % 
OpenCV       ██████████████▒░░░░░   75.95 % 
Docker       █████████▒░░░░░░░░░░   50.30 %
Others       █████▒░░░░░░░░░░░░░░   30.67 % 
Bash Script  ▓░░░░░░░░░░░░░░░░░░░   00.24 %

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