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License: Other
Package for KLayout to add integrated optics / silicon photonics functionality (waveguides, netlist extraction, circuit simulations, etc)
License: Other
If you run
Simulation>Show Compact Model in Lumerical Interconnect
and then Cancel it from the confirmation menu, the simulation still goes through.
We have already done this before a few years ago (gds2fdtd); it needs to be integrated / redone.
Create a compact model using 3D-FDTD:
Waveguide hotkey should not show GUI, instead use 'current configuration'
This means GUI parameters must be initialized BEFORE gui.show()
Do we need a development branch for SiEPIC-Tools? Can we just use master?
Right now, master is the old one (essentially 0.2.0) and not working..
Limitation in Verification: we assume that the layout was created by SiEPIC-Tools in KLayout, that PCells are there, and that the layout hasn't been flattened. This allows us to isolate individual components, and get their parameters. Working with a flattened layout would be harder, and require:
Hi Brett,
I discovered that you introduced a bug in the arc function, when you changed it. Namely the arc wasn't stopping exactly at the correct angle. This would introduce tiny gaps between arcs that are supposed to be connected. Did CMC find DRC errors in your layouts, with small gaps?
Anyways, I spent a long time debugging, and more or less returned it to what it was before...
Can you check your functions / PCells that rely on it to make sure it still works for your cases?
Action class cannot be reassigned, throws an exception, submitting a bug to KLayout.
Implement empty function in examples.py
Example that can be used as reference:
https://github.com/bpoulse/SiEPIC_EBeam_PDK/blob/master/klayout_dot_config/pymacros/Layout%20-%20IME%202017.lym
Convert previous generate_short_spice_files() function netlist trimming into:
# Inputs, and example of how to generate them:
# nets, components = topcell.identify_nets()
# selected_component = components[5] (elsewhere the desired component is selected)
def trim_netlist (nets, components, selected_component)
return trimmed_nets, trimmed_components
Presently it is a Lym file within each PDK. Presumably it should be shared.
Working on moving to pymacros in SiEPIC-Tools (dev branch)
When converting a waveguide to a path, the width of the waveguide should be read from the PCell and passed on to the new path. (implementation is in EBeam v0.1.x).
When used in the following PCell instead of layout_arc_wg_dbu , i'm seeing the following:
Implement function in examples.py
Example that can be used as reference:
https://github.com/bpoulse/SiEPIC_EBeam_PDK/blob/master/klayout_dot_config/pymacros/Layout%20-%20IME%202017.lym
Implement empty function in examples.py
Example that can be used as reference:
https://github.com/bpoulse/SiEPIC_EBeam_PDK/blob/master/klayout_dot_config/pymacros/Layout%20-%20IME%202017.lym
might be possible:
https://www.klayout.de/forum/comments.php?DiscussionID=744&page=1#Item_21
In scripts.py (for the most part, can just call waveguide_to_path then waveguide_from_path, but each waveguide type must be remembered)
Implement function for running monte carlo simulation
For devs knowledge base:
https://github.com/lukasc-ubc/SiEPIC-Tools/blob/master/klayout_dot_config/python/SiEPIC/utils.py#L29
When called, i.e. in https://github.com/lukasc-ubc/SiEPIC_EBeam_PDK/blob/v0.3.0/klayout_dot_config/tech/EBeam/pymacros/SiEPIC_EBeam%20Library.lym#L127
This error also occurs when called for any other technology
Implement a netlist creation function using Class Net
https://docs.python.org/2/library/tempfile.html
The user of mkdtemp() is responsible for deleting the temporary directory and its contents when done with it.
Add to KLayout, when exiting, delete this folder. FDTD project files are large...
In scripts.py (much the same as path snapping in extend.py)
during circuit sim / spice export
In scripts.py
Check that all pins are connected
returns null in setup.py
would be useful for debugging for component makers
pin rec, text, etc...
and pin direction so that they are leaving the component.
Change from full path to relative
@jaspreetj (perhaps?)
I have it working on Mac OSX. Could someone get this working for Windows?
See SiEPIC.lumerical.interconnect.Setup_Lumerical_KLayoutPython_integration() and SiEPIC.lumerical.interconnect.launch()
thank you
Lukas
Actual form is implemented using ui file. Needs logic.
For MC script, only get_parameters etc must be called
I understand the use of py files, since you can import them. But the debugger and "singleton-like" behaviour means we need to exit KLayout each time changes are made to py files.
Can we minimize the use of py files?
Lym files work well in the debugger where you can see the error, breakpoints, etc.
Waveguide PCell
When used in:
Implement function for launching lumerical
Check waveguides for basic errors
@lukasc-ubc @jaspreetj @mustafacc
Has anyone noticed an issue with PCells in KLayout 0.25 like below?
When inserting a new PCell, the instance does not show up in the hierarchy where it has been placed. In this example, I tried to add a Lumerical Laser to the cell v1.
Created a new menu: Measurement Data. Fetch data from GitHub and plot. Working on OSX/Windows, but presently only downloads the files and opens the PDFs.
Need a GUI to:
line 1004 in extend. causing an INTC crash.
a Ring_Modulator_DB_0_elec1a Ring_Modulator_DB_0_elec1c Ring_Modulator_DB_0_elec2h1 Ring_Modulator_DB_0_elec2h2 gc_detector1 gc_laser a sch_x=-1 sch_y=-1 sch_r=270
N1 Ring_Modulator_DB_0_elec1a 0 dcsource amplitude=0 sch_x=-2.1 sch_y=-1.875
N2 Ring_Modulator_DB_0_elec1c 0 dcsource amplitude=0 sch_x=-2.2 sch_y=-1.75
N3 Ring_Modulator_DB_0_elec2h1 0 dcsource amplitude=0 sch_x=-2.3 sch_y=-1.625
N4 Ring_Modulator_DB_0_elec2h2 0 dcsource amplitude=0 sch_x=-2.4 sch_y=-1.5
I don't what changed. But yesterday the hotkeys were working, and were automatically loaded.
Sometime tonight they stopped. Have to run manually "SiEPIC installation and initalization", each time a new layout is created or a new GDS file is loaded.
Data structure that can be used for various verification functions and netlist creation
ENHANCING core.py => Class Map
Using generated netlist, create spice file
Launch an INTERCONNECT simulation using the opt_in label:
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