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linguist

Language Savant. If your repository's language is being reported incorrectly, send us a pull request!

m64-a2teroids

A2teroids for Mapache 64

maxcut-unitintervalgraphs

This app allows for rapid testing of algorithm ideas.

muxes

nes_controller_interface

NES Controller Interface written in Verilog-2005

openradar

An open source library for interacting with and processing radar data, specialized for MIMO mmWave radars

presents

py65

Emulate 6502-based microcomputer systems in Python

riscv-assembler

RISC-V Assembly code assembler package for Python.

rustyperalta.github.io

schematics

Examples of how to Generate Schematics from SystemVerilog Synthesis Tools

shadowbox

sifferman.github.io

Personal website

stm32-spatial_audio

Replication of Apple's "Spatial Audio" with STM32

structs

Examples of how to use structures in IEEE 1800 SystemVerilog.

style-guides

lowRISC Style Guides

surround_sound

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

sv2v

SystemVerilog to Verilog conversion

tangnano_example

Simple example of how to get started with the Tang Nano with FuseSoC.

thesis

Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

transistor_schematics

This project creates transistor schematics for the sky130 PDK.

tt_asic_screensaver

ucsb_ece120b_sram

uvm-example

verilator

Verilator open-source SystemVerilog simulator and lint system

verilator_example

verilog-brainfuzz-interpreter

verilog_autograder

verilog_template

A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.