My name is Suhas Kudlur Viswanath and I am an avid enthusiast of open Instruction Set Architectures like RISC-V. I mainly develop RTL for processors using the RISC-V ISA, some more RTL for data-centric architectures like PIM and some sw on the side to aid with the above.
skudlur / cayde Goto Github PK
View Code? Open in Web Editor NEWcayde is 32-bit RISC-V core written in SystemVerilog
License: MIT License