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UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
Hi @SocialistDalao ,
I can't find the signal "rresp" in the file my_axi_interface.v.
And I can't understand below codes:
`RVALID: begin
if(rvalid == `False_v && rready == `False_v && rdata_valid_o == `True_v)begin
rnext_state = `AXI_IDLE;
end else begin
rnext_state = `RVALID;
end
end
Maybe itβs a bit special when you deal with the last data from slaver ?
Could u help me :D
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