General:

• could be useful to add to the wiki that KiCad 5 (under development) should allow to flip the PCB view; this will make easier to find/check components on the bottom side. This new feature was mentioned at FOSDEM 2017, I did not try KiCad 5 yet.
• for those manually assembling an H-L v2 from a bare PCB, a separate top-components BOM and bottom-components BOM will be useful. I extracted the top/bottom info from the KiCad "PCB Footprint Report" with a simple python script and manually marked with a different color every component on the BOM. Maybe your scripts could be modified to print the references in the BOM e.g. in red for the components on the top and in green for the ones on the bottom so there will still be a single BOM but it will be immediately clear where a component goes. This can avoid flipping the PCB too many times or easing placing all the components on one side first for those using reflow.

Schematic:

• U12 should be marked DNI ?
• is there a reason to have connection dots on the lines to DB2, DB16 and DB4?

BOM:

• J29 has a space in front of the reference text in the BOM (just wondering why)

PCB:

• C12 reference positioning on silkscreen unclear (maybe there was no space for a connecting line)
• D8-D11 polarity on PCB unclear (I see no polarity indication in their silkscreen)
• R54 refdes partially over pad
• B70 refdes partially over via
• B22 1v2 via maybe too close to B29, for manual assembly
  The problem here is that vias are not tented, which is great for a prototype, since one has many test points for "free" but for (manual) reflow may lead to some issues.
  On my PCB, after reflow I found several capacitors which were "skewed" toward the untented via, probably because of solder sucked by the via and/or surface tension during reflow moving the component in that direction. I then used too much solder paste and had several shorts due to this. I understand it may not be an issue for a proper reflow process but I wonder if in a "production" run via near pads (or even in general) should be tented.
  Same as above for
  • B10, C3 and B4
  • B9, B3 and B14
  • B18 and B30 - but they are on same net, GND (I just got the caps stuck together during soldering)
  • B19 and B33 - but they are on same net, GND
  • B11 and B16 - but they are on same net, GND
• C48, C150 could be in 0603 (like the other 10 uF caps) instead of 0805?
• X1 has no pin 1 dot/indication on silkscreen
• D1 should be CDSOD323-T05LC (bidirectional); its footprint on PCB is fine for an unidirectional device but will not for a bidirectional one (it shows a polarity line, bidirectional devices do not have a polarity line on case)
• L33, L34 (actually 0 ohm for a "standard build") can be 0603 like the other 0 ohm resistors in the BOM

Testing:

• on the wiki, for the leds.jic test, which 2 of the 4 are lit ? (is it random ?)

There are still some places in beta2 where the silkscreen is not clear. For example, around the clock generator U6.

Create pdf files of just the silkscreen at 2x enlargement to check. Post these pdfs for builders without KiCAD access to use when identifying components.

The default standard I2C address for CN7 (band select) is 0x20.

The diodes D8, D9, D10 and D11 are removed, and U18 is configured as four followers.

See post https://groups.google.com/d/msg/hermes-lite/1M7IdEku60U/_WGwC57HEgAJ from Claudio

Hello,

I was doing some more experiments on the RX input and noticed that probably the value of C55 needs to be corrected to compensate for the input capacitance of the AD9866. The differential input capacitance, from the datasheet, is 4 pF, which is then multiplied by 8 by the input transformer T2 so it looks like 32 pF on the 50 ohm side; this value needs to be subtracted from the theoretical 100 pF needed. We could then use 68 pF for C55 but for some reason things look a bit better when moving the whole capacitance after the transformer, removing C55 and placing 8.2 pF across the AD9866 RX inputs.

In the graph below is the measured wideband response for the default values (same as in the previous post) and when replacing C55 with 8.2 pF on the differential RX pins:

the notch moves a little higher in frequency (in the middle of the FM band) and the final rejection is a little higher, maybe because the transformer leakage inductance adds some filtering effect.

Looking at the passband response, there is a slight change on the upper end of the HF, maybe some fraction of a dB less loss at 30 MHz (as usual, ignore the small dips on the red trace, these were due to an issue in the measurement script)

the input impedance also looks a bit better, as the return loss above 10 MHz is improved:

https://groups.google.com/d/msg/hermes-lite/xJK3CdW_uV0/1ZSSs5A8AQAJ

R55 was changed from 75 to 120 Ohm to reduce the output of the opamp so that the PA is not over driven. This change did not make it into the beta3 BOM. With 75 Ohm, the output is 20dBm. R55 must be changed to 120 Ohm or care must be taken to not over drive the PA by reducing the TX Dac output level.

Stew observed variations in HL2 current usage. Look for these variations in my prototypes. Document what expected current consumption should be.

In the H-L v2b2 the TX relay toggles at power-up, while the FPGA is being configured. Similarly, the bias source for the PA, U14, is briefly enabled. May not be harmful but would be good to add a pull down (as R125, which should likely be mounted by default).
I find the relay clicking a bit annoying because it makes the user think that the unit went into TX unexpectedly.

For compatibility with HL1.22, the ethernet MAC PLL is buried inside the MAC rtl. It is much clearer and simpler to have this PLL at the toplevel.

Mark pin 2 of CN7 (FPGA 30) as "SDA" and pin 3 (FPGA 31) as "SCL".

https://github.com/softerhardware/Hermes-Lite2/wiki/Build-Notes-2.0beta3#add-resistors-for-proper-pe4259-switching

Footprints to be left in place so that traces can be cut to have real jumper if ever needed.

The holes on the PCB for the dual-purpose power connector are too small for the power pole connectors specified in the BOM. The holes must be enlarged.

The current BOM only includes the preferred part for any line item. There are more alternatives in the master database. These should be exposed in the BOM so that builders can better see and understand the options.

Reverse them.

Add a 10 uF capacitor to the input of Q1.

Label VPA+ with target 9.44V on schematic.
Label input power supply requirements and +/- on PCB silkscreen.

The primary X2 on the BOM has 6 pins. Only the 4 outer pins are used and the 2 inner pins are no connect. The footprint is such that it is easy to short one of the outer pins with an inner pin. Adjust the footprint to make this less likely. Also, the primary X2 has no pads that wrap around the edge for easy hand soldering. I resorted to hot air for this (which worked well). The current X2 is preferred as it is the most stable. Consider specifying/recommending a 4-pin variant also on the BOM for any hand builds.

The holes for TO-220 devices get in the way of using an aluminum block below the PA transistors as an alternate heat transfer path. Modify the PA device footprints so that TO-220 device leads must be bent and therefore no through holes. Make sure there is enough area with only ground exposed so that an reasonable size aluminum block may be used.

The ethernet connector LEDs are very dim. The 4 general purpose LEDs are very bright. Consider tweaking resistor values for more current for ethernet connector LEDs and less for general purpose LEDs.

See data from Claudio: https://groups.google.com/forum/#!topic/hermes-lite/1M7IdEku60U

Test that external PTT driven by Q5 works.

There are two similar devices Q2 NUD3124 and Q5 2N7002K. I would like to merge these BOM lines. The 2N7002K is less expensive. Can it be used for Q2?

Beta2 was fabricated without ENIG finish. It worked fine, but for hand-built ENIG may be better. I did pull one pad and destroy one trace that I had to fix with a manual mod.

Ask Elecrow to supply FEP wire with an order. See

https://groups.google.com/d/msg/hermes-lite/xJK3CdW_uV0/8ccoHYdeAAAJ

There needs to be a better way to measure the current to the power amp so that we can set the bias.

Handle errors in firmware

In beta2, corner holes support metric M2.5 but the hole for pressure on the PA transistors is M2. Consider increasing this hole to M2.5 to simplify nut/bolt/standoff requirements.

Bugs may have crept into the DSP chain. Simulation of the DSP blocks at max,min,normal values as well as reponse extraction would be good.

https://groups.google.com/d/msg/hermes-lite/fiU-WWNll80/H6EA0cAmBgAJ

See:

https://groups.google.com/d/msg/hermes-lite/_BAiRyqGvJk/GZsyNuuNBAAJ

The current HL2 RTL forked before Jim added better VNA support. Backport Jim's changes into HL2.

https://github.com/softerhardware/Hermes-Lite2/wiki/Build-Notes-2.0beta3#remove-opamp-from-current-and-temperature-sense-paths

See

https://groups.google.com/d/msg/hermes-lite/PM1fHZNECS4/Cdzv8tFKAAAJ

and other posts in that same thread.

The FPGA EEPROM U1 on some BOMs is specified as the wide package. The footprints on the PCB expects 3.9mm width. All BOMs in circulation should be updated.

Beta2 has tabs to support two enclosure widths. The intent is that these tabs may be broken off for use with the narrower enclosure width. The beta2 boards were fabricated without V-cuts to make this break-off easy. Also, the enclosure listed in the BOM has a slot that is not tall enough for a 1.6mm thick PCB. Support for multiple enclosure widths needs to be cleaned up. Possibilities are:

Work with Elecrow so that V-cuts are on the next batches of boards, and use a 1mm thick PCB (no extra cost) instead of 1.6mm. This option is attractive as PCB weight will be reduced for shipment and 0.05 spacing inexpensive headers/receptacles can be used for end launch connection to the filter board.

Scrap the narrow enclosure option, but then the BOM must be updated with a 10mm length of the current 15mm length enclosure. The 15mm length is commonly available, but the 10mm length is supposedly available for special order. I prefer relying on commonly available enclosures.

Some schematics out in the wild have an incorrect voltage divider (swapped resistor values) for the 1.2V power supply. R14 should be 10K and R15 should be 20K. R14 is the resistor in parallel with C19.

To facilitate testing the power supplies isolated from the design, consider ferrite bead or jumpers on all switching regulator output pins.

Some resistor and capacitor values may be modified to reduce the total number of BOM lines.

In places where higher voltage capacitors are required, consider using sizes even larger than 0805 to reduce cost.

Consider using higher voltage capacitors in more locations to reduce ESR.

It can be confusing to have the same value of resistor or capacitor but in different packages in different spots. Try to simplify this.

Add four TVS at CN4. Or document the need for TVS at panel mount connectors.

The current PCB has some footprints with invalid openings for the solder stencil. All footprints need to be reviewed and valid solder stencil footprints verified, corrected or created. For example, larger ICs will have a grid of openings, but beta2 footprints have just a single large opening. This is required for any sort of mass production.

As a first step, create a bit file that properly programs the i2c clock generator.

As a longterm solution, add support for a wishbone communication structure to all i2c and spi clients so that they can be accessed via software over a ethernet connection sidechannel.

https://groups.google.com/d/msg/hermes-lite/4s9wzStwCyY/4t9T7F57BgAJ

The current .sdc constraints file specifies some multicycle paths in the Ethernet MAC. There appears to be no min delay for these paths. These paths need to be understood and 100% properly constrained. It may be that just some builds are hitting the proper timing targets here and the Ethernet MAC will become flaky once more logic is added. Phil mentioned that Altera was helping him with these paths. I should also follow-up with Phil to see what Altera recommended.

The HL2 ethernet RTL forked from the openHPSDR version over a year ago. It is now quite different to support the old protocol and we can't just switch to what openHPSDR has. All changes made to the openHPSDR since we forked should be reviewed and incorporated into the HL2 version if of value.

Use firmware version numbers 40 and up for HermesLite version 2.

The HL2beta2 KiCAD files still depend on a few components in the KiCAD libraries. Sometimes these libraries change or are hard to install for a user. Any external library dependencies should be copied into the hermes lite libraries so that KiCAD files are more portable, not subject to library changes, and easier for users to setup.

Layout traces to the enable pins on the 1.2 and 3.3V regulators such that they can be cut and a wire connected easily. This is to support companion cards which may want to switch these supplies on and off.

As discussed here, it would be nice to be able to switch to half duplex to (hopefully) improve RX performances and to full duplex when needed (Puresignal, etc.).