Comments (3)
The IEEE standard states "White space shall be allowed between the text macro name and the left parenthesis in the macro usage.". Unfortunately the standard is generally silent about where comments are allowed, but unless explicitly stated otherwise (e.g. for the `line directive), I would assume that comments are allowed wherever white space is allowed. Note that unlike C/C++, the compiler directives are part of the language, so I think comments should be removed before the macro is substituted. And a new line is white space, so that is allowed.
I'm fairly sure NC-Verilog used to accept this. Testing on EDA playground, GPL CVer does accept it. And Aldec Riveria will accept a block comment in that place, just not a one-line comment. I don't have an account on EDA playground, so can't test the other commercial simulators.
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Do you see any potential thing which could be broken because of support of comment on such a place?
It seems to me that there is no ambiguity, the '(' is never optional. Hopefully this does not affect line number in expanded macro.
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I still do not know where block comment on this place should ended after preprocessing, but let's close this issue as it is not problem in this repo.
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Related Issues (5)
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