Comments (2)
katyo
commented on August 23, 2024
I tried to set correct PLLMUL but it doesn't help.
Strange, I have no problems with project in C where I setup clock in a next way:
RCC_CR |= (RCC_CR_HSEON | RCC_CR_CSSON);
for (; !((RCC_CR & (RCC_CR_HSERDY))); );
RCC_CFGR = (RCC_CFGR & ~(RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC))
| (RCC_CFGR_SW_HSE | RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE_DIV1 | RCC_CFGR_PLLMUL_MUL6 | RCC_CFGR_PLLSRC_HSE);
FLASH_ACR |= (FLASH_ACR_LATENCY_1WS);
RCC_CR |= (RCC_CR_PLLON);
for (; !((RCC_CR & (RCC_CR_PLLRDY))); );
RCC_CFGR = (RCC_CFGR & ~(RCC_CFGR_SW))
| (RCC_CFGR_SW_PLL);from stm32f0xx-hal.
pigrew
commented on August 23, 2024
I've created a patch that has the extra logic for determining the divider when HSI is the source. It's in my branch https://github.com/pigrew/stm32f0xx-hal/tree/pllsrc
I still need to test it (though it does pass the CI checks)... I'll create a PR once I'm more confident in it.
from stm32f0xx-hal.
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from stm32f0xx-hal.