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axi4_interconnect

AXI总线连接器

axi_ethernet_bridge

A bridge IP for interconnecting Xilinx's AXI Ethernet Subsystems (used with EthernetFMC).

bigmath

Project for testing and developing HW-implementations of integer operations. mult, mod, add, div etc.

biriscv

32-bit Superscalar RISC-V CPU

blabla

Implementation of the BlaBla version of the ChaCha stream cipher

blake2

Hardware implementation of the blake2 hash function

blake2s

Verilog implementation of the 32-bit version of the Blake2 hash function

blake3

Hardware implementation of the Blake3 hash function

booth_wallace_multiplier

Booth encoded Wallace tree multiplier

bsv_tutorial_cn

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

ca_prng

Cellular Automata based PRNG

cbc

CBC block cipher mode of operation for AES.

ccm

ccm mode hardware implementation

cdc-handshake-synchronizer

cfu-playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.

chacha

Verilog 2001 implementation of the ChaCha stream cipher.

chacha20-poly1305

Hardware implementation of the ChaCha20-Poly1305 AEAD construction

chaskey

Verilog implementation of the Chaskey lightweight message authentication code (MAC) function.

clock_multiplexed_fifo

cmac

Implementation of the CMAC keyed hash function using AES as block cipher.

cnn-accelerator-vlsi

Convolutional accelerator kernel, target ASIC & FPGA

cnn-fpga

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

cnna

A generic Convolutional Neural Network (CNN) Accelerator (CNNA) for FPGA

cocotbext-pcie

PCI express simulation framework for Cocotb

complex_sinusoid_ddfs_verilog

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

coretest

Test structure for cores developed as part of the Cryptech Open HSM project

coretest_bp_entropy

Coretest system for testing the FPGA based entropy source by Berndt Paysan.

coretest_test_core

The coretest module combined with the test_core as a test module.

corundum

Open source FPGA-based NIC and platform for in-network compute